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f80117f21c
* Recycling of megous v5.16.4 patches The patches were sorted as far as possible. Some patches are renamed according to their place of application. The length of the patch name has been changed to improve readability using the `git format-patch --filename-max-length=75` method. The folder containing the patches will have the name `patches.name` and the corresponding file `series.name` for the convenience of processing and moving them upstream. But the control file remains `series.conf`. Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> * Add a series of armbian patches for 5.16 Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> * Remove patches whose fixes are already in the kernel Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
156 lines
4.7 KiB
Diff
156 lines
4.7 KiB
Diff
From 1382c059f98f40a314709c7e5f02f1826fd8c7c8 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 4 Aug 2021 09:13:41 -0400
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Subject: [PATCH 241/446] PCI: dwc: rockchip: add legacy interrupt support
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The legacy interrupts on the rk356x pcie controller are handled by a
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single muxed interrupt. Add irq domain support to the pcie-dw-rockchip
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driver to support the virtual domain.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 ++++++++++++++++++-
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1 file changed, 89 insertions(+), 3 deletions(-)
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diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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index 916ef44db..616a6a0a7 100644
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--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -10,9 +10,12 @@
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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+#include <linux/irqchip/chained_irq.h>
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+#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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+#include <linux/of_irq.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@@ -36,10 +39,12 @@
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#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
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#define PCIE_L0S_ENTRY 0x11
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#define PCIE_CLIENT_GENERAL_CONTROL 0x0
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+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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+#define PCIE_LEGACY_INT_ENABLE GENMASK(7, 0)
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+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
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struct rockchip_pcie {
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@@ -51,6 +56,7 @@ struct rockchip_pcie {
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struct reset_control *rst;
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struct gpio_desc *rst_gpio;
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struct regulator *vpcie3v3;
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+ struct irq_domain *irq_domain;
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};
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static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
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@@ -65,6 +71,68 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip,
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writel_relaxed(val, rockchip->apb_base + reg);
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}
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+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
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+{
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
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+ struct device *dev = rockchip->pci.dev;
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+ u32 reg;
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+ u32 hwirq;
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+ u32 virq;
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+
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+ chained_irq_enter(chip, desc);
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+
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+ reg = rockchip_pcie_readl_apb(rockchip, 0x8);
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+
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+ while (reg) {
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+ hwirq = ffs(reg) - 1;
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+ reg &= ~BIT(hwirq);
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+
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+ virq = irq_find_mapping(rockchip->irq_domain, hwirq);
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+ if (virq)
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+ generic_handle_irq(virq);
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+ else
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+ dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
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+ }
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+
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+ chained_irq_exit(chip, desc);
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+}
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+
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+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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+ irq_hw_number_t hwirq)
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+{
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+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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+ irq_set_chip_data(irq, domain->host_data);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops intx_domain_ops = {
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+ .map = rockchip_pcie_intx_map,
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+};
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+
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+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
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+{
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+ struct device *dev = rockchip->pci.dev;
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+ struct device_node *intc;
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+
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+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
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+ if (!intc) {
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+ dev_err(dev, "missing child interrupt-controller node\n");
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+ return -EINVAL;
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+ }
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+
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+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
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+ &intx_domain_ops, rockchip);
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+ of_node_put(intc);
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+ if (!rockchip->irq_domain) {
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+ dev_err(dev, "failed to get a INTx IRQ domain\n");
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
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{
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rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
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@@ -111,9 +179,27 @@ static int rockchip_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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- u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
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+ struct device *dev = rockchip->pci.dev;
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+ int irq, ret;
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+ u32 val;
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+
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+ irq = of_irq_get_byname(dev->of_node, "legacy");
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+ if (irq < 0)
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+ return irq;
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+
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+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip);
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+
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+ ret = rockchip_pcie_init_irq_domain(rockchip);
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+ if (ret < 0)
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+ dev_err(dev, "failed to init irq domain\n");
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+
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+ /* enable legacy interrupts */
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+ val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE);
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+ val &= ~PCIE_LEGACY_INT_ENABLE;
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+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY);
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/* LTSSM enable control mode */
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+ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
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rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
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rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
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--
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2.31.1
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