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e7377248b3
* Bump Meson64 EDGE to 5.13 * Bump Rockchip64 EDGE to 5.13.y * Bump Odroid Xu4 edge to 5.13.y * Bump rockchip edge to 5.13.y
26 lines
1.1 KiB
Diff
26 lines
1.1 KiB
Diff
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
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index ce1d2446f..38447441b 100644
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--- a/drivers/clk/rockchip/clk-rk3399.c
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+++ b/drivers/clk/rockchip/clk-rk3399.c
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@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
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RK3399_CLKGATE_CON(8), 11, GFLAGS),
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- MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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+ MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
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COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
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diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
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index 44e0a319f..b7b07dfda 100644
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--- a/include/dt-bindings/clock/rk3399-cru.h
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+++ b/include/dt-bindings/clock/rk3399-cru.h
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@@ -19,6 +19,7 @@
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#define ARMCLKB 9
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/* sclk gates (special clocks) */
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+#define SCLK_I2SOUT_SRC 64
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#define SCLK_I2C1 65
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#define SCLK_I2C2 66
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#define SCLK_I2C3 67
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