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150ac0c2af
AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index 27954085..3c76c670 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
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.num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
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};
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+static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
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+ .common = &pll_cpux_clk.common,
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+ /* copy from pll_cpux_clk */
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+};
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+
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+static struct ccu_mux_nb sun50i_a64_cpu_nb = {
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+ .common = &cpux_clk.common,
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+ .cm = &cpux_clk.mux,
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+ .delay_us = 1, /* > 8 clock cycles at 24 MHz */
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+ .bypass_index = 1, /* index of 24 MHz oscillator */
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+};
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+
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static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *reg;
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u32 val;
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+ int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, res);
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@@ -897,7 +912,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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- return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
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+ ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
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+
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+ /* Gate then ungate PLL CPU after any rate changes */
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+ ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
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+
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+ /* Reparent CPU during PLL CPU rate changes */
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+ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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+ &sun50i_a64_cpu_nb);
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+
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+ return ret;
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}
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static const struct of_device_id sun50i_a64_ccu_ids[] = {
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