mirror of
https://github.com/armbian/build.git
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- add imx8m familie - add MBa8MPxL and MBa8MPxL-RAS314 Boards (based on imx8m) Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
1966 lines
61 KiB
Diff
1966 lines
61 KiB
Diff
From 3e31c704f76a785b87ddd9e99f975dbc9e100de7 Mon Sep 17 00:00:00 2001
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From: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
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Date: Wed, 10 Jan 2024 13:10:39 +0100
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Subject: [PATCH] Add HDMI support for IMX8MP
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- squash patches from Lucas Stach
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- buildfixes
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Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com>
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---
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.../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 79 ++
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.../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 69 ++
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.../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 62 +
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arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 27 +
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arch/arm64/boot/dts/freescale/imx8mp.dtsi | 133 ++
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drivers/gpu/drm/bridge/imx/Kconfig | 16 +
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drivers/gpu/drm/bridge/imx/Makefile | 3 +
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drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c | 202 +++
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drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c | 140 +++
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drivers/phy/freescale/Kconfig | 6 +
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drivers/phy/freescale/Makefile | 1 +
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drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1078 +++++++++++++++++
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12 files changed, 1816 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
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create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
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create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
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create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
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create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
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create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
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diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
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new file mode 100644
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index 000000000000..aa369721ac99
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
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@@ -0,0 +1,79 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Freescale i.MX8MP HDMI Parallel Video Interface
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+
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+maintainers:
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+ - Lucas Stach <l.stach@pengutronix.de>
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+
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+description: |
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+ The HDMI parallel video interface is a timing and sync generator block in the
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+ i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
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+
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+properties:
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+ compatible:
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+ enum:
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+ - fsl,imx8mp-hdmi-pvi
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+
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+ reg:
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+ maxItems: 1
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+
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+ power-domains:
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+ maxItems: 1
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+
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+ ports:
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+ $ref: /schemas/graph.yaml#/properties/ports
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+
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+ properties:
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+ port@0:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description: Input from the LCDIF controller.
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+
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+ port@1:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description: Output to the HDMI TX controller
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+
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+ required:
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+ - port@0
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+ - port@1
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+
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+required:
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+ - compatible
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+ - reg
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+ - power-domains
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+ - ports
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/imx8mp-clock.h>
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+ #include <dt-bindings/power/imx8mp-power.h>
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+
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+ display-bridge@32fc4000 {
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+ compatible = "fsl,imx8mp-hdmi-pvi";
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+ reg = <0x32fc4000 0x40>;
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ pvi_from_lcdif3: endpoint {
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+ remote-endpoint = <&lcdif3_to_pvi>;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ pvi_to_hdmi_tx: endpoint {
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+ remote-endpoint = <&hdmi_tx_from_pvi>;
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+ };
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+ };
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+ };
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+ };
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diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
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new file mode 100644
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index 000000000000..75ebeaa8c9d5
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
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@@ -0,0 +1,69 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Freescale i.MX8MP DWC HDMI TX Encoder
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+
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+maintainers:
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+ - Lucas Stach <l.stach@pengutronix.de>
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+
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+description: |
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+ The i.MX8MP HDMI transmitter is a Synopsys DesignWare
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+ HDMI 2.0 TX controller IP.
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+
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+allOf:
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+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
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+
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+properties:
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+ compatible:
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+ enum:
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+ - fsl,imx8mp-hdmi
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+
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+ reg-io-width:
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+ const: 1
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+
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+ clocks:
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+ maxItems: 5
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+
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+ clock-names:
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+ items:
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+ - const: iahb
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+ - const: isfr
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+ - const: fdcc
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+ - const: cec
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+ - const: pix
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+
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+ power-domains:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - interrupts
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+ - power-domains
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/interrupt-controller/irq.h>
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+ #include <dt-bindings/clock/imx8mp-clock.h>
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+ #include <dt-bindings/power/imx8mp-power.h>
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+
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+ hdmi@32fd8000 {
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+ compatible = "fsl,imx8mp-hdmi";
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+ reg = <0x32fd8000 0x7eff>;
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+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
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+ <&clk IMX8MP_CLK_HDMI_FDCC_TST>,
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+ <&clk IMX8MP_CLK_32K>,
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+ <&hdmi_tx_phy>;
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+ clock-names = "iahb", "isfr", "fdcc", "cec", "pix";
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
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+ reg-io-width = <1>;
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+ };
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diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
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new file mode 100644
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index 000000000000..bc21c073e92a
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
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@@ -0,0 +1,62 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Freescale i.MX8MP HDMI PHY binding
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+
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+maintainers:
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+ - Lucas Stach <l.stach@pengutronix.de>
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+
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+properties:
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+ compatible:
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+ enum:
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+ - fsl,imx8mp-hdmi-phy
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#clock-cells":
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+ const: 0
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+
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+ clocks:
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+ minItems: 2
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+ maxItems: 2
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+
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+ clock-names:
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+ items:
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+ - const: apb
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+ - const: ref
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+
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+ "#phy-cells":
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+ const: 0
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+
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+ power-domains:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - "#clock-cells"
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+ - clocks
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+ - clock-names
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+ - power-domains
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/imx8mp-clock.h>
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+ #include <dt-bindings/power/imx8mp-power.h>
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+
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+ phy@32fdff00 {
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+ compatible = "fsl,imx8mp-hdmi-phy";
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+ reg = <0x32fdff00 0x100>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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+ <&clk IMX8MP_CLK_HDMI_24M>;
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+ clock-names = "apb", "ref";
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
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+ #clock-cells = <0>;
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+ #phy-cells = <0>;
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+ };
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diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
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index cc9d468b43ab..e20e0a0d99fd 100644
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--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
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+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
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@@ -299,6 +299,20 @@ &flexcan2 {
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status = "disabled";/* can2 pin conflict with pdm */
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};
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+&hdmi_pvi {
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+ status = "okay";
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+};
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+
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+&hdmi_tx {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_hdmi>;
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+ status = "okay";
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+};
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+
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+&hdmi_tx_phy {
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+ status = "okay";
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+};
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+
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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@@ -509,6 +523,10 @@ dsi_out: endpoint {
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};
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};
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+&lcdif3 {
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+ status = "okay";
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+};
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+
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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clocks = <&pcie0_refclk>;
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@@ -718,6 +736,15 @@ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
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>;
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};
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+ pinctrl_hdmi: hdmigrp {
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+ fsl,pins = <
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+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
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+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
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+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
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+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
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+ >;
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+ };
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+
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
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diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
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index 4b50920ac204..b00b4cced57c 100644
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--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
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+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@@ -832,6 +832,23 @@ pgc_mediamix: power-domain@10 {
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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};
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+ pgc_hdmimix: power-domains@14 {
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+ #power-domain-cells = <0>;
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+ reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
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+ <&clk IMX8MP_CLK_HDMI_APB>;
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+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
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+ <&clk IMX8MP_CLK_HDMI_APB>;
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+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
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+ <&clk IMX8MP_SYS_PLL1_133M>;
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+ assigned-clock-rates = <500000000>, <133000000>;
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+ };
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+
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+ pgc_hdmi_phy: power-domains@15 {
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+ #power-domain-cells = <0>;
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+ reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
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+ };
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+
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pgc_mipi_phy2: power-domain@16 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
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@@ -1831,6 +1848,122 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
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#power-domain-cells = <1>;
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#clock-cells = <0>;
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};
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+
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+ hdmi_blk_ctrl: blk-ctrl@32fc0000 {
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+ compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
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+ reg = <0x32fc0000 0x23c>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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+ <&clk IMX8MP_CLK_HDMI_ROOT>,
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+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
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+ <&clk IMX8MP_CLK_HDMI_24M>;
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+ clock-names = "apb", "axi", "ref_266m", "ref_24m";
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+ power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
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+ <&pgc_hdmimix>, <&pgc_hdmimix>,
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+ <&pgc_hdmimix>, <&pgc_hdmimix>,
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+ <&pgc_hdmimix>, <&pgc_hdmi_phy>,
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+ <&pgc_hdmimix>, <&pgc_hdmimix>;
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+ power-domain-names = "bus", "irqsteer", "lcdif",
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+ "pai", "pvi", "trng",
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+ "hdmi-tx", "hdmi-tx-phy",
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+ "hdmiblk-hrv", "hdmiblk-hdcp";
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+ #power-domain-cells = <1>;
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+ };
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+
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+ irqsteer_hdmi: interrupt-controller@32fc2000 {
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+ compatible = "fsl,imx-irqsteer";
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+ reg = <0x32fc2000 0x44>;
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+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ fsl,channel = <1>;
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+ fsl,num-irqs = <64>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_APB>;
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+ clock-names = "ipg";
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
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+ };
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+
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+ hdmi_pvi: display-bridge@32fc4000 {
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+ compatible = "fsl,imx8mp-hdmi-pvi";
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+ reg = <0x32fc4000 0x40>;
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ pvi_from_lcdif3: endpoint {
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+ remote-endpoint = <&lcdif3_to_pvi>;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ pvi_to_hdmi_tx: endpoint {
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+ remote-endpoint = <&hdmi_tx_from_pvi>;
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+ };
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+ };
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+ };
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+ };
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+
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+ lcdif3: display-controller@32fc6000 {
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+ compatible = "fsl,imx8mp-lcdif";
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+ reg = <0x32fc6000 0x238>;
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+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-parent = <&irqsteer_hdmi>;
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+ clocks = <&hdmi_tx_phy>,
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+ <&clk IMX8MP_CLK_HDMI_APB>,
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+ <&clk IMX8MP_CLK_HDMI_ROOT>;
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+ clock-names = "pix", "axi", "disp_axi";
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+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
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+ status = "disabled";
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+
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+ port {
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+ lcdif3_to_pvi: endpoint {
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+ remote-endpoint = <&pvi_from_lcdif3>;
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+ };
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+ };
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+ };
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+
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+ hdmi_tx: hdmi@32fd8000 {
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+ compatible = "fsl,imx8mp-hdmi";
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+ reg = <0x32fd8000 0x7eff>;
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+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-parent = <&irqsteer_hdmi>;
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+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
|
|
+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
|
|
+ <&clk IMX8MP_CLK_HDMI_FDCC_TST>,
|
|
+ <&clk IMX8MP_CLK_32K>,
|
|
+ <&hdmi_tx_phy>;
|
|
+ clock-names = "iahb", "isfr", "fdcc", "cec", "pix";
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
|
|
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
|
|
+ reg-io-width = <1>;
|
|
+ status = "disabled";
|
|
+
|
|
+ port {
|
|
+ hdmi_tx_from_pvi: endpoint {
|
|
+ remote-endpoint = <&pvi_to_hdmi_tx>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdmi_tx_phy: phy@32fdff00 {
|
|
+ compatible = "fsl,imx8mp-hdmi-phy";
|
|
+ reg = <0x32fdff00 0x100>;
|
|
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
|
|
+ <&clk IMX8MP_CLK_HDMI_24M>;
|
|
+ clock-names = "apb", "ref";
|
|
+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
|
|
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
|
|
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
|
|
+ #clock-cells = <0>;
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
pcie: pcie@33800000 {
|
|
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
|
|
index 9fae28db6aa7..b1f4d962b2af 100644
|
|
--- a/drivers/gpu/drm/bridge/imx/Kconfig
|
|
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
|
|
@@ -49,4 +49,20 @@ config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
|
|
Choose this to enable pixel link to display pixel interface(PXL2DPI)
|
|
found in Freescale i.MX8qxp processor.
|
|
|
|
+config DRM_IMX8MP_DW_HDMI_BRIDGE
|
|
+ tristate "i.MX8MP HDMI bridge support"
|
|
+ depends on OF
|
|
+ depends on COMMON_CLK
|
|
+ select DRM_DW_HDMI
|
|
+ help
|
|
+ Choose this to enable support for the internal HDMI encoder found
|
|
+ on the i.MX8MP SoC.
|
|
+
|
|
+config DRM_IMX8MP_HDMI_PVI
|
|
+ tristate "i.MX8MP HDMI PVI bridge support"
|
|
+ depends on OF
|
|
+ help
|
|
+ Choose this to enable support for the internal HDMI TX Parallel
|
|
+ Video Interface found on the i.MX8MP SoC.
|
|
+
|
|
endif # ARCH_MXC || COMPILE_TEST
|
|
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
|
|
index 8e2ebf3399a1..373beb358df3 100644
|
|
--- a/drivers/gpu/drm/bridge/imx/Makefile
|
|
+++ b/drivers/gpu/drm/bridge/imx/Makefile
|
|
@@ -4,3 +4,6 @@ obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
|
|
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
|
|
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
|
|
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
|
|
+
|
|
+obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi.o
|
|
+obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o
|
|
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
|
|
new file mode 100644
|
|
index 000000000000..30d40c21dabb
|
|
--- /dev/null
|
|
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
|
|
@@ -0,0 +1,202 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+
|
|
+/*
|
|
+ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
|
+ */
|
|
+
|
|
+#include <drm/drm_atomic_helper.h>
|
|
+#include <drm/drm_bridge.h>
|
|
+#include <drm/drm_crtc.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/of_device.h>
|
|
+#include <linux/of_graph.h>
|
|
+#include <linux/pm_runtime.h>
|
|
+
|
|
+#define HTX_PVI_CTL 0x0
|
|
+#define PVI_CTL_OP_VSYNC_POL BIT(18)
|
|
+#define PVI_CTL_OP_HSYNC_POL BIT(17)
|
|
+#define PVI_CTL_OP_DE_POL BIT(16)
|
|
+#define PVI_CTL_INP_VSYNC_POL BIT(14)
|
|
+#define PVI_CTL_INP_HSYNC_POL BIT(13)
|
|
+#define PVI_CTL_INP_DE_POL BIT(12)
|
|
+#define PVI_CTL_INPUT_LCDIF BIT(2)
|
|
+#define PVI_CTL_EN BIT(0)
|
|
+
|
|
+struct imx8mp_hdmi_pvi {
|
|
+ struct drm_bridge bridge;
|
|
+ struct device *dev;
|
|
+ struct drm_bridge *next_bridge;
|
|
+ void __iomem *regs;
|
|
+};
|
|
+
|
|
+static inline struct imx8mp_hdmi_pvi *
|
|
+to_imx8mp_hdmi_pvi(struct drm_bridge *bridge)
|
|
+{
|
|
+ return container_of(bridge, struct imx8mp_hdmi_pvi, bridge);
|
|
+}
|
|
+
|
|
+static int imx8mp_hdmi_pvi_bridge_attach(struct drm_bridge *bridge,
|
|
+ enum drm_bridge_attach_flags flags)
|
|
+{
|
|
+ struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge);
|
|
+
|
|
+ return drm_bridge_attach(bridge->encoder, pvi->next_bridge,
|
|
+ bridge, flags);
|
|
+}
|
|
+
|
|
+static void imx8mp_hdmi_pvi_bridge_enable(struct drm_bridge *bridge,
|
|
+ struct drm_bridge_state *bridge_state)
|
|
+{
|
|
+ struct drm_atomic_state *state = bridge_state->base.state;
|
|
+ struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge);
|
|
+ struct drm_connector_state *conn_state;
|
|
+ const struct drm_display_mode *mode;
|
|
+ struct drm_crtc_state *crtc_state;
|
|
+ struct drm_connector *connector;
|
|
+ u32 bus_flags, val;
|
|
+
|
|
+ connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
|
|
+ conn_state = drm_atomic_get_new_connector_state(state, connector);
|
|
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
|
|
+
|
|
+ if (WARN_ON(pm_runtime_resume_and_get(pvi->dev)))
|
|
+ return;
|
|
+
|
|
+ mode = &crtc_state->adjusted_mode;
|
|
+
|
|
+ val = PVI_CTL_INPUT_LCDIF;
|
|
+
|
|
+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
+ val |= PVI_CTL_OP_VSYNC_POL | PVI_CTL_INP_VSYNC_POL;
|
|
+
|
|
+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
+ val |= PVI_CTL_OP_HSYNC_POL | PVI_CTL_INP_HSYNC_POL;
|
|
+
|
|
+ if (pvi->next_bridge->timings)
|
|
+ bus_flags = pvi->next_bridge->timings->input_bus_flags;
|
|
+ else if (bridge_state)
|
|
+ bus_flags = bridge_state->input_bus_cfg.flags;
|
|
+
|
|
+ if (bus_flags & DRM_BUS_FLAG_DE_HIGH)
|
|
+ val |= PVI_CTL_OP_DE_POL | PVI_CTL_INP_DE_POL;
|
|
+
|
|
+ writel(val, pvi->regs + HTX_PVI_CTL);
|
|
+ val |= PVI_CTL_EN;
|
|
+ writel(val, pvi->regs + HTX_PVI_CTL);
|
|
+}
|
|
+
|
|
+static void imx8mp_hdmi_pvi_bridge_disable(struct drm_bridge *bridge,
|
|
+ struct drm_bridge_state *bridge_state)
|
|
+{
|
|
+ struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge);
|
|
+
|
|
+ writel(0x0, pvi->regs + HTX_PVI_CTL);
|
|
+
|
|
+ pm_runtime_put(pvi->dev);
|
|
+}
|
|
+
|
|
+static u32 *imx8mp_hdmi_pvi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
|
|
+ struct drm_bridge_state *bridge_state,
|
|
+ struct drm_crtc_state *crtc_state,
|
|
+ struct drm_connector_state *conn_state,
|
|
+ u32 output_fmt,
|
|
+ unsigned int *num_input_fmts)
|
|
+{
|
|
+ struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge);
|
|
+ struct drm_bridge *next_bridge = pvi->next_bridge;
|
|
+ struct drm_bridge_state *next_state;
|
|
+
|
|
+ if (!next_bridge->funcs->atomic_get_input_bus_fmts)
|
|
+ return 0;
|
|
+
|
|
+ next_state = drm_atomic_get_new_bridge_state(crtc_state->state,
|
|
+ next_bridge);
|
|
+
|
|
+ return next_bridge->funcs->atomic_get_input_bus_fmts(next_bridge,
|
|
+ next_state,
|
|
+ crtc_state,
|
|
+ conn_state,
|
|
+ output_fmt,
|
|
+ num_input_fmts);
|
|
+}
|
|
+
|
|
+static const struct drm_bridge_funcs imx_hdmi_pvi_bridge_funcs = {
|
|
+ .attach = imx8mp_hdmi_pvi_bridge_attach,
|
|
+ .atomic_enable = imx8mp_hdmi_pvi_bridge_enable,
|
|
+ .atomic_disable = imx8mp_hdmi_pvi_bridge_disable,
|
|
+ .atomic_get_input_bus_fmts = imx8mp_hdmi_pvi_bridge_get_input_bus_fmts,
|
|
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
|
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
|
+ .atomic_reset = drm_atomic_helper_bridge_reset,
|
|
+};
|
|
+
|
|
+static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device_node *remote;
|
|
+ struct imx8mp_hdmi_pvi *pvi;
|
|
+
|
|
+ pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
|
|
+ if (!pvi)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ platform_set_drvdata(pdev, pvi);
|
|
+ pvi->dev = &pdev->dev;
|
|
+
|
|
+ pvi->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
+ if (IS_ERR(pvi->regs))
|
|
+ return PTR_ERR(pvi->regs);
|
|
+
|
|
+ /* Get the next bridge in the pipeline. */
|
|
+ remote = of_graph_get_remote_node(pdev->dev.of_node, 1, -1);
|
|
+ if (!remote)
|
|
+ return -EINVAL;
|
|
+
|
|
+ pvi->next_bridge = of_drm_find_bridge(remote);
|
|
+ of_node_put(remote);
|
|
+
|
|
+ if (!pvi->next_bridge)
|
|
+ return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
|
|
+ "could not find next bridge\n");
|
|
+
|
|
+ /* Register the bridge. */
|
|
+ pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
|
|
+ pvi->bridge.of_node = pdev->dev.of_node;
|
|
+ pvi->bridge.timings = pvi->next_bridge->timings;
|
|
+
|
|
+ drm_bridge_add(&pvi->bridge);
|
|
+
|
|
+ pm_runtime_enable(&pdev->dev);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int imx8mp_hdmi_pvi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct imx8mp_hdmi_pvi *pvi = platform_get_drvdata(pdev);
|
|
+
|
|
+ drm_bridge_remove(&pvi->bridge);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id imx8mp_hdmi_pvi_match[] = {
|
|
+ {
|
|
+ .compatible = "fsl,imx8mp-hdmi-pvi",
|
|
+ }, {
|
|
+ /* sentinel */
|
|
+ },
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, imx8mp_hdmi_pvi_match);
|
|
+
|
|
+static struct platform_driver imx8mp_hdmi_pvi_driver = {
|
|
+ .probe = imx8mp_hdmi_pvi_probe,
|
|
+ .remove = imx8mp_hdmi_pvi_remove,
|
|
+ .driver = {
|
|
+ .name = "imx-hdmi-pvi",
|
|
+ .of_match_table = imx8mp_hdmi_pvi_match,
|
|
+ },
|
|
+};
|
|
+module_platform_driver(imx8mp_hdmi_pvi_driver);
|
|
+
|
|
+MODULE_DESCRIPTION("i.MX8MP HDMI TX Parallel Video Interface bridge driver");
|
|
+MODULE_LICENSE("GPL");
|
|
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
|
|
new file mode 100644
|
|
index 000000000000..06849b817aed
|
|
--- /dev/null
|
|
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
|
|
@@ -0,0 +1,140 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+
|
|
+/*
|
|
+ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
|
+ */
|
|
+
|
|
+#include <drm/bridge/dw_hdmi.h>
|
|
+#include <drm/drm_modes.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/mod_devicetable.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/platform_device.h>
|
|
+
|
|
+struct imx8mp_hdmi {
|
|
+ struct dw_hdmi_plat_data plat_data;
|
|
+ struct dw_hdmi *dw_hdmi;
|
|
+ struct clk *pixclk;
|
|
+ struct clk *fdcc;
|
|
+};
|
|
+
|
|
+static enum drm_mode_status
|
|
+imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
|
|
+ const struct drm_display_info *info,
|
|
+ const struct drm_display_mode *mode)
|
|
+{
|
|
+ struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data;
|
|
+
|
|
+ if (mode->clock < 13500)
|
|
+ return MODE_CLOCK_LOW;
|
|
+
|
|
+ if (mode->clock > 297000)
|
|
+ return MODE_CLOCK_HIGH;
|
|
+
|
|
+ if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
|
|
+ mode->clock * 1000)
|
|
+ return MODE_CLOCK_RANGE;
|
|
+
|
|
+ /* We don't support double-clocked and Interlaced modes */
|
|
+ if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
|
|
+ (mode->flags & DRM_MODE_FLAG_INTERLACE))
|
|
+ return MODE_BAD;
|
|
+
|
|
+ return MODE_OK;
|
|
+}
|
|
+
|
|
+static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
|
|
+ const struct drm_display_info *display,
|
|
+ const struct drm_display_mode *mode)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
|
|
+{
|
|
+}
|
|
+
|
|
+static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
|
|
+{
|
|
+ /*
|
|
+ * Just release PHY core from reset, all other power management is done
|
|
+ * by the PHY driver.
|
|
+ */
|
|
+ dw_hdmi_phy_gen1_reset(hdmi);
|
|
+
|
|
+ dw_hdmi_phy_setup_hpd(hdmi, data);
|
|
+}
|
|
+
|
|
+static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
|
|
+ .init = imx8mp_hdmi_phy_init,
|
|
+ .disable = imx8mp_hdmi_phy_disable,
|
|
+ .setup_hpd = im8mp_hdmi_phy_setup_hpd,
|
|
+ .read_hpd = dw_hdmi_phy_read_hpd,
|
|
+ .update_hpd = dw_hdmi_phy_update_hpd,
|
|
+};
|
|
+
|
|
+static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct dw_hdmi_plat_data *plat_data;
|
|
+ struct imx8mp_hdmi *hdmi;
|
|
+ int ret;
|
|
+
|
|
+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
|
|
+ if (!hdmi)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ plat_data = &hdmi->plat_data;
|
|
+
|
|
+ hdmi->pixclk = devm_clk_get(dev, "pix");
|
|
+ if (IS_ERR(hdmi->pixclk))
|
|
+ return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
|
|
+ "Unable to get pixel clock\n");
|
|
+
|
|
+ hdmi->fdcc = devm_clk_get_enabled(dev, "fdcc");
|
|
+ if (IS_ERR(hdmi->fdcc))
|
|
+ return dev_err_probe(dev, PTR_ERR(hdmi->fdcc),
|
|
+ "Unable to get FDCC clock\n");
|
|
+
|
|
+ plat_data->mode_valid = imx8mp_hdmi_mode_valid;
|
|
+ plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
|
|
+ plat_data->phy_name = "SAMSUNG HDMI TX PHY";
|
|
+ plat_data->priv_data = hdmi;
|
|
+
|
|
+ hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
|
|
+ if (IS_ERR(hdmi->dw_hdmi))
|
|
+ return PTR_ERR(hdmi->dw_hdmi);
|
|
+
|
|
+ platform_set_drvdata(pdev, hdmi);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int imx8mp_dw_hdmi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct imx8mp_hdmi *hdmi = platform_get_drvdata(pdev);
|
|
+
|
|
+ dw_hdmi_remove(hdmi->dw_hdmi);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
|
|
+ { .compatible = "fsl,imx8mp-hdmi" },
|
|
+ { /* Sentinel */ },
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, imx8mp_dw_hdmi_of_table);
|
|
+
|
|
+static struct platform_driver imx8mp_dw_hdmi_platform_driver = {
|
|
+ .probe = imx8mp_dw_hdmi_probe,
|
|
+ .remove = imx8mp_dw_hdmi_remove,
|
|
+ .driver = {
|
|
+ .name = "imx8mp-dw-hdmi",
|
|
+ .of_match_table = imx8mp_dw_hdmi_of_table,
|
|
+ },
|
|
+};
|
|
+
|
|
+module_platform_driver(imx8mp_dw_hdmi_platform_driver);
|
|
+
|
|
+MODULE_DESCRIPTION("i.MX8MP HDMI encoder driver");
|
|
+MODULE_LICENSE("GPL");
|
|
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
|
|
index 853958fb2c06..5c2b73042dfc 100644
|
|
--- a/drivers/phy/freescale/Kconfig
|
|
+++ b/drivers/phy/freescale/Kconfig
|
|
@@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE
|
|
Enable this to add support for the PCIE PHY as found on
|
|
i.MX8M family of SOCs.
|
|
|
|
+config PHY_FSL_SAMSUNG_HDMI_PHY
|
|
+ tristate "Samsung HDMI PHY support"
|
|
+ depends on OF && HAS_IOMEM
|
|
+ help
|
|
+ Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
|
|
+
|
|
endif
|
|
|
|
config PHY_FSL_LYNX_28G
|
|
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
|
|
index cedb328bc4d2..dbcafdcc8751 100644
|
|
--- a/drivers/phy/freescale/Makefile
|
|
+++ b/drivers/phy/freescale/Makefile
|
|
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
|
|
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
|
|
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
|
|
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
|
|
+obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
|
|
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
|
|
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
|
|
new file mode 100644
|
|
index 000000000000..6d20a5ce44e6
|
|
--- /dev/null
|
|
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
|
|
@@ -0,0 +1,1078 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+/*
|
|
+ * Copyright 2020 NXP
|
|
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
|
+ */
|
|
+
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/iopoll.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/of_device.h>
|
|
+#include <linux/of.h>
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/pm_runtime.h>
|
|
+
|
|
+#define HDMI_TX_CONTROL0 0x200
|
|
+#define HDMI_TX_CONTROL_PHY_PWRDWN BIT(3)
|
|
+
|
|
+#define PHY_REG_33 0x84
|
|
+#define REG33_MODE_SET_DONE BIT(7)
|
|
+#define REG33_FIX_DA BIT(1)
|
|
+
|
|
+#define PHY_REG_34 0x88
|
|
+#define REG34_PHY_READY BIT(7)
|
|
+#define REG34_PLL_LOCK BIT(6)
|
|
+#define REG34_PHY_CLK_READY BIT(5)
|
|
+
|
|
+
|
|
+#define PHY_PLL_REGS_NUM 48
|
|
+
|
|
+struct phy_config {
|
|
+ u32 clk_rate;
|
|
+ u8 regs[PHY_PLL_REGS_NUM];
|
|
+};
|
|
+
|
|
+const struct phy_config phy_pll_cfg[] = {
|
|
+ { 22250000, {
|
|
+ 0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 23750000, {
|
|
+ 0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ },{
|
|
+ 24000000, {
|
|
+ 0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ },{
|
|
+ 24024000, {
|
|
+ 0x00, 0xD1, 0x50, 0xF1, 0x99, 0x02, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x00, 0x25, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 25175000, {
|
|
+ 0x00, 0xD1, 0x54, 0xFC, 0xCC, 0x91, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF5, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 25200000, {
|
|
+ 0x00, 0xD1, 0x54, 0xF0, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF4, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 26750000, {
|
|
+ 0x00, 0xD1, 0x5A, 0xF2, 0x89, 0x88, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE6, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 27000000, {
|
|
+ 0x00, 0xD1, 0x5A, 0xF0, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 27027000, {
|
|
+ 0x00, 0xD1, 0x5A, 0xF2, 0xFD, 0x0C, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 29500000, {
|
|
+ 0x00, 0xD1, 0x62, 0xF4, 0x95, 0x08, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xD1, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 30750000, {
|
|
+ 0x00, 0xD1, 0x66, 0xF4, 0x82, 0x01, 0x88, 0x45,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC8, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 30888000, {
|
|
+ 0x00, 0xD1, 0x66, 0xF4, 0x99, 0x18, 0x88, 0x45,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC7, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 33750000, {
|
|
+ 0x00, 0xD1, 0x70, 0xF4, 0x82, 0x01, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB7, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 35000000, {
|
|
+ 0x00, 0xD1, 0x58, 0xB8, 0x8B, 0x88, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB0, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 36000000, {
|
|
+ 0x00, 0xD1, 0x5A, 0xB0, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 36036000, {
|
|
+ 0x00, 0xD1, 0x5A, 0xB2, 0xFD, 0x0C, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 40000000, {
|
|
+ 0x00, 0xD1, 0x64, 0xB0, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x9A, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 43200000, {
|
|
+ 0x00, 0xD1, 0x5A, 0x90, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 43243200, {
|
|
+ 0x00, 0xD1, 0x5A, 0x92, 0xFD, 0x0C, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 44500000, {
|
|
+ 0x00, 0xD1, 0x5C, 0x92, 0x98, 0x11, 0x84, 0x41,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8B, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 47000000, {
|
|
+ 0x00, 0xD1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x83, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 47500000, {
|
|
+ 0x00, 0xD1, 0x63, 0x96, 0xA1, 0x82, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x00, 0x82, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 50349650, {
|
|
+ 0x00, 0xD1, 0x54, 0x7C, 0xC3, 0x8F, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x10, 0xF5, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
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|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 209500000, {
|
|
+ 0x00, 0xD1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xEB, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 213000000, {
|
|
+ 0x00, 0xD1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE7, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 216000000, {
|
|
+ 0x00, 0xD1, 0x5A, 0x10, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 216216000, {
|
|
+ 0x00, 0xD1, 0x5A, 0x12, 0xFD, 0x0C, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 237600000, {
|
|
+ 0x00, 0xD1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xCF, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 254000000, {
|
|
+ 0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 277500000, {
|
|
+ 0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 288000000, {
|
|
+ 0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ }, {
|
|
+ 297000000, {
|
|
+ 0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45,
|
|
+ 0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80,
|
|
+ 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
|
|
+ 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
+ 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
+struct fsl_samsung_hdmi_phy {
|
|
+ struct device *dev;
|
|
+ void __iomem *regs;
|
|
+ struct clk *apbclk;
|
|
+ struct clk *refclk;
|
|
+
|
|
+ /* clk provider */
|
|
+ struct clk_hw hw;
|
|
+ const struct phy_config *cur_cfg;
|
|
+};
|
|
+
|
|
+static inline struct fsl_samsung_hdmi_phy *
|
|
+to_fsl_samsung_hdmi_phy(struct clk_hw *hw)
|
|
+{
|
|
+ return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
|
|
+}
|
|
+
|
|
+static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
|
|
+ const struct phy_config *cfg)
|
|
+{
|
|
+ int i, ret;
|
|
+ u8 val;
|
|
+
|
|
+ /* HDMI PHY init */
|
|
+ writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
|
|
+
|
|
+ for (i = 0; i < PHY_PLL_REGS_NUM; i++)
|
|
+ writeb(cfg->regs[i], phy->regs + i * 4);
|
|
+
|
|
+ writeb(REG33_FIX_DA | REG33_MODE_SET_DONE , phy->regs + PHY_REG_33);
|
|
+
|
|
+ ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
|
|
+ val & REG34_PLL_LOCK,
|
|
+ 50, 20000);
|
|
+ if (ret)
|
|
+ dev_err(phy->dev, "PLL failed to lock\n");
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,
|
|
+ unsigned long parent_rate)
|
|
+{
|
|
+ struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
|
|
+
|
|
+ if (!phy->cur_cfg)
|
|
+ return 74250000;
|
|
+
|
|
+ return phy->cur_cfg->clk_rate;
|
|
+}
|
|
+
|
|
+static long phy_clk_round_rate(struct clk_hw *hw,
|
|
+ unsigned long rate, unsigned long *parent_rate)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
|
|
+ if (phy_pll_cfg[i].clk_rate <= rate)
|
|
+ return phy_pll_cfg[i].clk_rate;
|
|
+
|
|
+ return -EINVAL;
|
|
+}
|
|
+
|
|
+static int phy_clk_set_rate(struct clk_hw *hw,
|
|
+ unsigned long rate, unsigned long parent_rate)
|
|
+{
|
|
+ struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
|
|
+ int i;
|
|
+
|
|
+ for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
|
|
+ if (phy_pll_cfg[i].clk_rate <= rate)
|
|
+ break;
|
|
+
|
|
+ if (i < 0)
|
|
+ return -EINVAL;
|
|
+
|
|
+ phy->cur_cfg = &phy_pll_cfg[i];
|
|
+
|
|
+ return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
|
|
+}
|
|
+
|
|
+static const struct clk_ops phy_clk_ops = {
|
|
+ .recalc_rate = phy_clk_recalc_rate,
|
|
+ .round_rate = phy_clk_round_rate,
|
|
+ .set_rate = phy_clk_set_rate,
|
|
+};
|
|
+
|
|
+static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
|
|
+{
|
|
+ struct device *dev = phy->dev;
|
|
+ struct device_node *np = dev->of_node;
|
|
+ struct clk_init_data init;
|
|
+ const char *parent_name;
|
|
+ struct clk *phyclk;
|
|
+ int ret;
|
|
+
|
|
+ parent_name = __clk_get_name(phy->refclk);
|
|
+
|
|
+ init.parent_names = &parent_name;
|
|
+ init.num_parents = 1;
|
|
+ init.flags = 0;
|
|
+ init.name = "hdmi_pclk";
|
|
+ init.ops = &phy_clk_ops;
|
|
+
|
|
+ phy->hw.init = &init;
|
|
+
|
|
+ phyclk = devm_clk_register(dev, &phy->hw);
|
|
+ if (IS_ERR(phyclk))
|
|
+ return dev_err_probe(dev, PTR_ERR(phyclk),
|
|
+ "failed to register clock\n");
|
|
+
|
|
+ ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk);
|
|
+ if (ret)
|
|
+ return dev_err_probe(dev, ret,
|
|
+ "failed to register clock provider\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct fsl_samsung_hdmi_phy *phy;
|
|
+ int ret;
|
|
+
|
|
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
|
|
+ if (!phy)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ platform_set_drvdata(pdev, phy);
|
|
+ phy->dev = &pdev->dev;
|
|
+
|
|
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
+ if (IS_ERR(phy->regs))
|
|
+ return PTR_ERR(phy->regs);
|
|
+
|
|
+ phy->apbclk = devm_clk_get(phy->dev, "apb");
|
|
+ if (IS_ERR(phy->apbclk))
|
|
+ return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
|
|
+ "failed to get apb clk\n");
|
|
+
|
|
+ phy->refclk = devm_clk_get(phy->dev, "ref");
|
|
+ if (IS_ERR(phy->refclk))
|
|
+ return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
|
|
+ "failed to get ref clk\n");
|
|
+
|
|
+ ret = clk_prepare_enable(phy->apbclk);
|
|
+ if (ret) {
|
|
+ dev_err(phy->dev, "failed to enable apbclk\n");
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ pm_runtime_get_noresume(phy->dev);
|
|
+ pm_runtime_set_active(phy->dev);
|
|
+ pm_runtime_enable(phy->dev);
|
|
+
|
|
+ ret = phy_clk_register(phy);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "register clk failed\n");
|
|
+ goto register_clk_failed;
|
|
+ }
|
|
+
|
|
+ pm_runtime_put(phy->dev);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+register_clk_failed:
|
|
+ clk_disable_unprepare(phy->apbclk);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)
|
|
+{
|
|
+ of_clk_del_provider(pdev->dev.of_node);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int fsl_samsung_hdmi_phy_suspend(struct device *dev)
|
|
+{
|
|
+ struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
|
|
+
|
|
+ clk_disable_unprepare(phy->apbclk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int fsl_samsung_hdmi_phy_resume(struct device *dev)
|
|
+{
|
|
+ struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
|
|
+ int ret = 0;
|
|
+
|
|
+ ret = clk_prepare_enable(phy->apbclk);
|
|
+ if (ret) {
|
|
+ dev_err(phy->dev, "failed to enable apbclk\n");
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ if (phy->cur_cfg)
|
|
+ ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
|
|
+
|
|
+ return ret;
|
|
+
|
|
+}
|
|
+#endif
|
|
+
|
|
+static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops = {
|
|
+ SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend,
|
|
+ fsl_samsung_hdmi_phy_resume, NULL)
|
|
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
+ pm_runtime_force_resume)
|
|
+};
|
|
+
|
|
+static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {
|
|
+ {
|
|
+ .compatible = "fsl,imx8mp-hdmi-phy",
|
|
+ }, {
|
|
+ /* sentinel */
|
|
+ }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);
|
|
+
|
|
+static struct platform_driver fsl_samsung_hdmi_phy_driver = {
|
|
+ .probe = fsl_samsung_hdmi_phy_probe,
|
|
+ .remove = fsl_samsung_hdmi_phy_remove,
|
|
+ .driver = {
|
|
+ .name = "fsl-samsung-hdmi-phy",
|
|
+ .of_match_table = fsl_samsung_hdmi_phy_of_match,
|
|
+ .pm = &fsl_samsung_hdmi_phy_pm_ops,
|
|
+ },
|
|
+};
|
|
+module_platform_driver(fsl_samsung_hdmi_phy_driver);
|
|
+
|
|
+MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
|
|
+MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");
|
|
+MODULE_LICENSE("GPL v2");
|
|
--
|
|
2.34.1
|
|
|