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d1186b8a0e
I have changed the way the patches are generated a bit. Instead of using orange-pi branch from megous tree for 6.6 kernel, I have used the following kernel branches a83t-suspend, af8133j, anx, audio, axp, cam, drm, err, fixes, mbus, modem, opi3, pb, pinetab, pp, ppkb, samuel, speed, tbs-a711, ths These branches were carefully chosen to include only allwinner related patches and remove importing of the rockchip related patches into the allwinner kernel. Following patches are modified to fix patch application failure - patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch - patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch - patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch - patches.armbian/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch - patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch - patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1.patch Following patches are modified because of kernel api change to fix compilation failure - patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch - patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
246 lines
8.5 KiB
Diff
246 lines
8.5 KiB
Diff
From 432246948309396204697a010342ba6a5a94f387 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sat, 9 Nov 2019 13:22:05 +0100
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Subject: [PATCH 035/170] drv:media:cedrus: hevc: Improve buffer management
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/staging/media/sunxi/cedrus/cedrus.h | 9 +-
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.../staging/media/sunxi/cedrus/cedrus_h265.c | 120 ++++++++++--------
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2 files changed, 70 insertions(+), 59 deletions(-)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
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index 0a17ed0dc..1b20e23ee 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
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@@ -107,6 +107,11 @@ struct cedrus_buffer {
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unsigned int position;
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enum cedrus_h264_pic_type pic_type;
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} h264;
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+ struct {
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+ void *mv_col_buf;
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+ dma_addr_t mv_col_buf_dma;
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+ ssize_t mv_col_buf_size;
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+ } h265;
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} codec;
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};
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@@ -140,10 +145,6 @@ struct cedrus_ctx {
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ssize_t intra_pred_buf_size;
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} h264;
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struct {
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- void *mv_col_buf;
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- dma_addr_t mv_col_buf_addr;
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- ssize_t mv_col_buf_size;
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- ssize_t mv_col_buf_unit_size;
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void *neighbor_info_buf;
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dma_addr_t neighbor_info_buf_addr;
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void *entry_points_buf;
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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index 685cb00de..55a1874c8 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@@ -91,26 +91,66 @@ static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
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static inline dma_addr_t
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cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
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- unsigned int index, unsigned int field)
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+ unsigned int index,
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+ const struct v4l2_ctrl_hevc_sps *sps)
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{
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- return ctx->codec.h265.mv_col_buf_addr + index *
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- ctx->codec.h265.mv_col_buf_unit_size +
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- field * ctx->codec.h265.mv_col_buf_unit_size / 2;
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+ struct cedrus_buffer *cedrus_buf = NULL;
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+ struct vb2_buffer *buf = NULL;
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+ struct vb2_queue *vq;
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+
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+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
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+ if (vq)
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+ buf = vb2_get_buffer(vq, index);
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+
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+ if (buf)
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+ cedrus_buf = vb2_to_cedrus_buffer(buf);
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+
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+ if (!cedrus_buf)
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+ return 0;
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+
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+ if (!cedrus_buf->codec.h265.mv_col_buf_size) {
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+ unsigned int ctb_size_luma, width_in_ctb_luma;
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+ unsigned int log2_max_luma_coding_block_size;
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+
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+ log2_max_luma_coding_block_size =
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+ sps->log2_min_luma_coding_block_size_minus3 + 3 +
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+ sps->log2_diff_max_min_luma_coding_block_size;
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+ ctb_size_luma = 1 << log2_max_luma_coding_block_size;
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+ width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples,
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+ ctb_size_luma);
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+
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+ cedrus_buf->codec.h265.mv_col_buf_size = ALIGN(width_in_ctb_luma *
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+ DIV_ROUND_UP(sps->pic_height_in_luma_samples, ctb_size_luma) *
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+ CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE, 1024);
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+
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+ cedrus_buf->codec.h265.mv_col_buf =
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+ dma_alloc_attrs(ctx->dev->dev,
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+ cedrus_buf->codec.h265.mv_col_buf_size,
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+ &cedrus_buf->codec.h265.mv_col_buf_dma,
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+ GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
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+
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+ if (!cedrus_buf->codec.h265.mv_col_buf) {
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+ cedrus_buf->codec.h265.mv_col_buf_size = 0;
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+ cedrus_buf->codec.h265.mv_col_buf_dma = 0;
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+ }
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+ }
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+
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+ return cedrus_buf->codec.h265.mv_col_buf_dma;
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}
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static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
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unsigned int index,
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bool field_pic,
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u32 pic_order_cnt[],
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- int buffer_index)
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+ int buffer_index,
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+ const struct v4l2_ctrl_hevc_sps *sps)
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{
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struct cedrus_dev *dev = ctx->dev;
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dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0);
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dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1);
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dma_addr_t mv_col_buf_addr[2] = {
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- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
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- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index,
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- field_pic ? 1 : 0)
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+ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps),
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+ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps)
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};
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u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO +
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VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index;
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@@ -134,7 +174,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
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static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
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const struct v4l2_hevc_dpb_entry *dpb,
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- u8 num_active_dpb_entries)
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+ u8 num_active_dpb_entries,
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+ const struct v4l2_ctrl_hevc_sps *sps)
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{
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struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
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V4L2_BUF_TYPE_VIDEO_CAPTURE);
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@@ -152,7 +193,7 @@ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
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cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic,
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pic_order_cnt,
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- buffer_index);
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+ buffer_index, sps);
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}
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}
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@@ -416,37 +457,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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width_in_ctb_luma =
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DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
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- /* MV column buffer size and allocation. */
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- if (!ctx->codec.h265.mv_col_buf_size) {
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- unsigned int num_buffers =
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- run->dst->vb2_buf.vb2_queue->num_buffers;
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-
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- /*
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- * Each CTB requires a MV col buffer with a specific unit size.
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- * Since the address is given with missing lsb bits, 1 KiB is
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- * added to each buffer to ensure proper alignment.
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- */
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- ctx->codec.h265.mv_col_buf_unit_size =
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- DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) *
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- DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) *
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- CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
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-
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- ctx->codec.h265.mv_col_buf_size = num_buffers *
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- ctx->codec.h265.mv_col_buf_unit_size;
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-
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- /* Buffer is never accessed by CPU, so we can skip kernel mapping. */
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- ctx->codec.h265.mv_col_buf =
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- dma_alloc_attrs(dev->dev,
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- ctx->codec.h265.mv_col_buf_size,
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- &ctx->codec.h265.mv_col_buf_addr,
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- GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
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- if (!ctx->codec.h265.mv_col_buf) {
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- ctx->codec.h265.mv_col_buf_size = 0;
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- // TODO: Abort the process here.
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- return;
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- }
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- }
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-
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/* Activate H265 engine. */
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cedrus_engine_enable(ctx, CEDRUS_CODEC_H265);
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@@ -702,7 +712,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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/* Write decoded picture buffer in pic list. */
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cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb,
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- decode_params->num_active_dpb_entries);
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+ decode_params->num_active_dpb_entries, sps);
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/* Output frame. */
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@@ -713,7 +723,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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cedrus_h265_frame_info_write_single(ctx, output_pic_list_index,
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slice_params->pic_struct != 0,
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pic_order_cnt,
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- run->dst->vb2_buf.index);
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+ run->dst->vb2_buf.index, sps);
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cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index);
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@@ -762,9 +772,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
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{
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struct cedrus_dev *dev = ctx->dev;
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- /* The buffer size is calculated at setup time. */
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- ctx->codec.h265.mv_col_buf_size = 0;
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-
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/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
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ctx->codec.h265.neighbor_info_buf =
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dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
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@@ -791,15 +798,6 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx)
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{
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struct cedrus_dev *dev = ctx->dev;
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- if (ctx->codec.h265.mv_col_buf_size > 0) {
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- dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size,
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- ctx->codec.h265.mv_col_buf,
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- ctx->codec.h265.mv_col_buf_addr,
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- DMA_ATTR_NO_KERNEL_MAPPING);
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-
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- ctx->codec.h265.mv_col_buf_size = 0;
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- }
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-
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dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
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ctx->codec.h265.neighbor_info_buf,
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ctx->codec.h265.neighbor_info_buf_addr,
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@@ -816,6 +814,17 @@ static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
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cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE);
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}
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+static void cedrus_h265_buf_cleanup(struct cedrus_ctx *ctx,
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+ struct cedrus_buffer *buf)
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+{
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+ if (buf->codec.h265.mv_col_buf_size)
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+ dma_free_attrs(ctx->dev->dev,
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+ buf->codec.h265.mv_col_buf_size,
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+ buf->codec.h265.mv_col_buf,
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+ buf->codec.h265.mv_col_buf_dma,
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+ DMA_ATTR_NO_KERNEL_MAPPING);
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+}
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+
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struct cedrus_dec_ops cedrus_dec_ops_h265 = {
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.irq_clear = cedrus_h265_irq_clear,
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.irq_disable = cedrus_h265_irq_disable,
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@@ -824,4 +833,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h265 = {
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.start = cedrus_h265_start,
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.stop = cedrus_h265_stop,
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.trigger = cedrus_h265_trigger,
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+ .buf_cleanup = cedrus_h265_buf_cleanup,
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};
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--
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2.35.3
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