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214 lines
6.9 KiB
Diff
214 lines
6.9 KiB
Diff
From e07ed986c1e7c280e556c6a070fddd70300e2aa1 Mon Sep 17 00:00:00 2001
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From: Dikshita Agarwal <quic_dikshita@quicinc.com>
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Date: Fri, 7 Feb 2025 13:24:46 +0530
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Subject: [PATCH] media: iris: implement the boot sequence of the firmware
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Set the memory region on the firmware and implement the boot sequence.
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Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345)
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Reviewed-by: Stefan Schmidt <stefan.schmidt@linaro.org>
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Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
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Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
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Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
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Link: https://lore.kernel.org/r/20250207-qcom-video-iris-v10-6-ab66eeffbd20@quicinc.com
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Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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---
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drivers/media/platform/qcom/iris/Makefile | 1 +
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drivers/media/platform/qcom/iris/iris_core.c | 7 ++
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.../platform/qcom/iris/iris_platform_common.h | 1 +
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.../platform/qcom/iris/iris_platform_sm8550.c | 3 +
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.../platform/qcom/iris/iris_vpu_common.c | 89 +++++++++++++++++++
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.../platform/qcom/iris/iris_vpu_common.h | 13 +++
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6 files changed, 114 insertions(+)
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create mode 100644 drivers/media/platform/qcom/iris/iris_vpu_common.c
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create mode 100644 drivers/media/platform/qcom/iris/iris_vpu_common.h
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diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
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index 6906caa2c481..792f1d6ac8f3 100644
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--- a/drivers/media/platform/qcom/iris/Makefile
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+++ b/drivers/media/platform/qcom/iris/Makefile
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@@ -6,5 +6,6 @@ iris-objs += iris_core.o \
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iris_platform_sm8550.o \
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iris_probe.o \
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iris_vidc.o \
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+ iris_vpu_common.o \
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obj-$(CONFIG_VIDEO_QCOM_IRIS) += iris.o
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diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c
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index 8c7d53c57086..5ad66ac113ae 100644
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--- a/drivers/media/platform/qcom/iris/iris_core.c
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+++ b/drivers/media/platform/qcom/iris/iris_core.c
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@@ -6,6 +6,7 @@
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#include "iris_core.h"
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#include "iris_firmware.h"
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#include "iris_state.h"
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+#include "iris_vpu_common.h"
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void iris_core_deinit(struct iris_core *core)
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{
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@@ -39,10 +40,16 @@ int iris_core_init(struct iris_core *core)
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if (ret)
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goto error_queue_deinit;
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+ ret = iris_vpu_boot_firmware(core);
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+ if (ret)
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+ goto error_unload_fw;
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+
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mutex_unlock(&core->lock);
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return 0;
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+error_unload_fw:
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+ iris_fw_unload(core);
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error_queue_deinit:
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iris_hfi_queues_deinit(core);
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error:
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diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
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index 42c1fe8e4fa6..7e661e8928bd 100644
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--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
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+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
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@@ -44,6 +44,7 @@ struct iris_platform_data {
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const char *fwname;
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u32 pas_id;
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struct tz_cp_config *tz_cp_config_data;
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+ u32 core_arch;
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};
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#endif
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diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c
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index bf389181d8cc..237f932946d6 100644
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--- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c
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+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c
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@@ -7,6 +7,8 @@
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#include "iris_hfi_gen2.h"
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#include "iris_platform_common.h"
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+#define VIDEO_ARCH_LX 1
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+
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static const struct icc_info sm8550_icc_table[] = {
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{ "cpu-cfg", 1000, 1000 },
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{ "video-mem", 1000, 15000000 },
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@@ -48,4 +50,5 @@ struct iris_platform_data sm8550_data = {
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.fwname = "qcom/vpu/vpu30_p4.mbn",
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.pas_id = IRIS_PAS_ID,
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.tz_cp_config_data = &tz_cp_config_sm8550,
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+ .core_arch = VIDEO_ARCH_LX,
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};
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diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
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new file mode 100644
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index 000000000000..959ed46e8f47
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--- /dev/null
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+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
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@@ -0,0 +1,89 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#include <linux/iopoll.h>
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+
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+#include "iris_core.h"
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+#include "iris_vpu_common.h"
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+
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+#define CPU_BASE_OFFS 0x000A0000
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+
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+#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
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+
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+#define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)
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+#define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)
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+
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+#define CTRL_ERROR_STATUS__M 0xfe
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+
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+#define QTBL_INFO (CPU_CS_BASE_OFFS + 0x50)
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+#define QTBL_ENABLE BIT(0)
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+
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+#define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54)
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+#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)
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+#define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C)
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+#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
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+#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
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+
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+#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
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+#define HOST2XTENSA_INTR_ENABLE BIT(0)
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+
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+#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
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+
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+static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core)
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+{
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+ u32 queue_size, value;
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+
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+ /* Iris hardware requires 4K queue alignment */
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+ queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) +
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+ (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K);
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+
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+ value = (u32)core->iface_q_table_daddr;
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+ writel(value, core->reg_base + UC_REGION_ADDR);
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+
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+ /* Iris hardware requires 1M queue alignment */
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+ value = ALIGN(SFR_SIZE + queue_size, SZ_1M);
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+ writel(value, core->reg_base + UC_REGION_SIZE);
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+
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+ value = (u32)core->iface_q_table_daddr;
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+ writel(value, core->reg_base + QTBL_ADDR);
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+
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+ writel(QTBL_ENABLE, core->reg_base + QTBL_INFO);
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+
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+ if (core->sfr_daddr) {
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+ value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch;
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+ writel(value, core->reg_base + SFR_ADDR);
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+ }
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+}
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+
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+int iris_vpu_boot_firmware(struct iris_core *core)
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+{
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+ u32 ctrl_init = BIT(0), ctrl_status = 0, count = 0, max_tries = 1000;
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+
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+ iris_vpu_setup_ucregion_memory_map(core);
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+
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+ writel(ctrl_init, core->reg_base + CTRL_INIT);
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+ writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
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+
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+ while (!ctrl_status && count < max_tries) {
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+ ctrl_status = readl(core->reg_base + CTRL_STATUS);
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+ if ((ctrl_status & CTRL_ERROR_STATUS__M) == 0x4) {
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+ dev_err(core->dev, "invalid setting for uc_region\n");
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+ break;
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+ }
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+
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+ usleep_range(50, 100);
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+ count++;
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+ }
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+
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+ if (count >= max_tries) {
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+ dev_err(core->dev, "error booting up iris firmware\n");
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+ return -ETIME;
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+ }
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+
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+ writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
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+ writel(0x0, core->reg_base + CPU_CS_X2RPMH);
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+
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+ return 0;
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+}
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diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
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new file mode 100644
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index 000000000000..bafcf46520fd
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--- /dev/null
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+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
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@@ -0,0 +1,13 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef __IRIS_VPU_COMMON_H__
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+#define __IRIS_VPU_COMMON_H__
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+
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+struct iris_core;
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+
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+int iris_vpu_boot_firmware(struct iris_core *core);
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+
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+#endif
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--
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2.34.1
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