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124 lines
3.9 KiB
Diff
124 lines
3.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: ssp97 <zhang@yuanpai.win>
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Date: Fri, 11 Apr 2025 23:35:49 +0800
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Subject: rk3308: fix uart dma.
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Signed-off-by: ssp97 <zhang@yuanpai.win>
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---
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arch/arm64/boot/dts/rockchip/rk3308.dtsi | 10 ++++++++++
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drivers/soc/rockchip/grf.c | 14 ++++++++++
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2 file changed, 24 insertions(+)
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diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
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index 5fd62046b..78138cee6 100644
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--- a/drivers/soc/rockchip/grf.c
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+++ b/drivers/soc/rockchip/grf.c
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@@ -84,10 +84,21 @@ static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
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static const struct rockchip_grf_info rk3328_grf __initconst = {
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.values = rk3328_defaults,
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.num_values = ARRAY_SIZE(rk3328_defaults),
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};
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+#define RK3308_GRF_SOC_CON3 0x30c
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+
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+static const struct rockchip_grf_value rk3308_defaults[] __initconst = {
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+ { "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) },
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+};
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+
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+static const struct rockchip_grf_info rk3308_grf __initconst = {
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+ .values = rk3308_defaults,
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+ .num_values = ARRAY_SIZE(rk3308_defaults),
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+};
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+
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#define RK3368_GRF_SOC_CON15 0x43c
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static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
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{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
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};
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@@ -147,10 +158,13 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
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.compatible = "rockchip,rk3288-grf",
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.data = (void *)&rk3288_grf,
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}, {
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.compatible = "rockchip,rk3328-grf",
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.data = (void *)&rk3328_grf,
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+ }, {
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+ .compatible = "rockchip,rk3308-grf",
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+ .data = (void *)&rk3308_grf,
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}, {
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.compatible = "rockchip,rk3368-grf",
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.data = (void *)&rk3368_grf,
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}, {
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.compatible = "rockchip,rk3399-grf",
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diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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index 7d1571e4f..a6b8dc8df 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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@@ -351,10 +351,12 @@ uart0: serial@ff0a0000 {
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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+ dmas = <&dmac0 4>, <&dmac0 5>;
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+ dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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@@ -364,10 +366,12 @@ uart1: serial@ff0b0000 {
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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+ dmas = <&dmac0 6>, <&dmac0 7>;
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+ dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
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status = "disabled";
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};
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@@ -377,10 +381,12 @@ uart2: serial@ff0c0000 {
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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+ dmas = <&dmac0 8>, <&dmac0 9>;
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+ dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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@@ -390,10 +396,12 @@ uart3: serial@ff0d0000 {
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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+ dmas = <&dmac0 10>, <&dmac0 11>;
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+ dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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};
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@@ -403,10 +411,12 @@ uart4: serial@ff0e0000 {
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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+ dmas = <&dmac1 18>, <&dmac1 19>;
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+ dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
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status = "disabled";
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};
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--
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Created with Armbian build tools https://github.com/armbian/build
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