mirrors/armbian_build
1
0
Fork 0
mirror of https://github.com/armbian/build.git synced 2025-08-15 07:36:57 +02:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity
2d9cce1846
armbian_build/patch/kernel/archive/rockchip64-6.16/rk3308-vop-output.patch
Werner fa9302f162
Some checks are pending
Forked Helper / 📢 Run repository dispatch on fork (push) Waiting to run
Details
Announce PR merge to Discord / announcepush (push) Waiting to run
Details
Scorecards Security Scan / Scorecards analysis (push) Waiting to run
Details
rockchip64: bump edge to 6.16-rc3 (#8328) 
* Fix wifi drivers on kernel v6.16

These patches can get deleted after merged upstream.

* initial commit

* fix header

* remove ssv6051 driver

---------

Co-authored-by: amazingfate <liujianfeng1994@gmail.com>
2025-06-24 15:25:34 +00:00

339 lines
12 KiB
Diff
Executable File
Raw Blame History

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com>
Date: Sat, 22 Feb 2025 09:22:52 +0000
Subject: rk3308: rk3308 vop output
Signed-off-by: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 110 ++++++++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 102 +++++++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 60 +++++
3 files changed, 272 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -143,6 +143,12 @@ arm-pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
mac_clkin: external-mac-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
@@ -697,6 +703,26 @@ dmac1: dma-controller@ff2d0000 {
#dma-cells = <1>;
};
+ vop: vop@ff2e0000 {
+ compatible = "rockchip,rk3308-vop";
+ reg = <0x0 0xff2e0000 0x0 0x1fc>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+ reset-names = "axi", "ahb", "dclk";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdc_ctl>;
+
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
i2s_8ch_0: i2s@ff300000 {
compatible = "rockchip,rk3308-i2s-tdm";
reg = <0x0 0xff300000 0x0 0x1000>;
@@ -2118,5 +2144,89 @@ uart4_rts_pin: uart4-rts-pin {
<4 RK_PA7 0 &pcfg_pull_none>;
};
};
+
+ lcdc {
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins =
+ /* dclk */
+ <1 RK_PA0 1 &pcfg_pull_none_12ma>,
+ /* hsync */
+ <1 RK_PA1 1 &pcfg_pull_none>,
+ /* vsync */
+ <1 RK_PA2 1 &pcfg_pull_none>,
+ /* den */
+ <1 RK_PA3 1 &pcfg_pull_none>,
+ /* d0 */
+ <1 RK_PA4 1 &pcfg_pull_none>,
+ /* d1 */
+ <1 RK_PA5 1 &pcfg_pull_none>,
+ /* d2 */
+ <1 RK_PA6 1 &pcfg_pull_none>,
+ /* d3 */
+ <1 RK_PA7 1 &pcfg_pull_none>,
+ /* d4 */
+ <1 RK_PB0 1 &pcfg_pull_none>,
+ /* d5 */
+ <1 RK_PB1 1 &pcfg_pull_none>,
+ /* d6 */
+ <1 RK_PB2 1 &pcfg_pull_none>,
+ /* d7 */
+ <1 RK_PB3 1 &pcfg_pull_none>,
+ /* d8 */
+ <1 RK_PB4 1 &pcfg_pull_none>,
+ /* d9 */
+ <1 RK_PB5 1 &pcfg_pull_none>,
+ /* d10 */
+ <1 RK_PB6 1 &pcfg_pull_none>,
+ /* d11 */
+ <1 RK_PB7 1 &pcfg_pull_none>,
+ /* d12 */
+ <1 RK_PC0 1 &pcfg_pull_none>,
+ /* d13 */
+ <1 RK_PC1 1 &pcfg_pull_none>,
+ /* d14 */
+ <1 RK_PC2 1 &pcfg_pull_none>,
+ /* d15 */
+ <1 RK_PC3 1 &pcfg_pull_none>,
+ /* d16 */
+ <1 RK_PC4 1 &pcfg_pull_none>,
+ /* d17 */
+ <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ lcdc_rgb888_m0: lcdc-rgb888-m0 {
+ rockchip,pins =
+ /* d18 */
+ <1 RK_PC6 6 &pcfg_pull_none>,
+ /* d19 */
+ <1 RK_PC7 6 &pcfg_pull_none>,
+ /* d20 */
+ <2 RK_PB1 3 &pcfg_pull_none>,
+ /* d21 */
+ <2 RK_PB2 3 &pcfg_pull_none>,
+ /* d22 */
+ <2 RK_PB7 3 &pcfg_pull_none>,
+ /* d23 */
+ <2 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ lcdc_rgb888_m1: lcdc-rgb888-m1 {
+ rockchip,pins =
+ /* d18 */
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ /* d19 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* d20 */
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ /* d21 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* d22 */
+ <3 RK_PB2 4 &pcfg_pull_none>,
+ /* d23 */
+ <3 RK_PB3 4 &pcfg_pull_none>;
+ };
+ };
+
+
};
};
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -1186,6 +1186,106 @@ static const struct vop_data rk3328_vop = {
.max_output = { 4096, 2160 },
};
+static const struct vop_intr rk3308_lit_intr = {
+ .intrs = rk3368_vop_intrs,
+ .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+ .line_flag_num[0] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 0),
+ .line_flag_num[1] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 16),
+ .status = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_STATUS, 0xffff, 0),
+ .enable = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_EN, 0xffff, 0),
+ .clear = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_CLEAR, 0xffff, 0),
+};
+
+static const struct vop_output rk3308_ctrl_data = {
+ .rgb_en = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 0),
+ .rgb_pin_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x7, 2),
+ .rgb_dclk_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 1),
+};
+
+static const struct vop_common rk3308_common = {
+ .standby = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 1),
+ .cfg_done = VOP_REG(RK3308_LIT_REG_CFG_DONE, 0x1, 0),
+ .dsp_blank = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 14),
+ .dither_down_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 8),
+ .dither_down_sel = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 7),
+ .dither_down_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 6),
+ .dither_up = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 2),
+ .dsp_lut_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 5),
+ .gate_en = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 0),
+ .out_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0xf, 16),
+};
+
+static const struct vop_scl_regs rk3308_lit_win_scl = {
+ .scale_yrgb_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+ .scale_yrgb_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+ .scale_cbcr_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+ .scale_cbcr_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
+static const struct vop_win_phy rk3308_lit_win0_data = {
+ .scl = &rk3308_lit_win_scl,
+ .data_formats = formats_win_full,
+ .nformats = ARRAY_SIZE(formats_win_full),
+
+ .enable = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 12),
+ .act_info = VOP_REG(RK3308_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
+ .dsp_info = VOP_REG(RK3308_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
+ .dsp_st = VOP_REG(RK3308_LIT_WIN0_DSP_ST, 0xffffffff, 0),
+ .yrgb_mst = VOP_REG(RK3308_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
+ .uv_mst = VOP_REG(RK3308_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
+ .yrgb_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 0),
+ .uv_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 16),
+
+ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 2),
+ .alpha_mode = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
+ .alpha_en = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
+};
+
+static const struct vop_win_phy rk3308_lit_win1_data = {
+ .data_formats = formats_win_lite,
+ .nformats = ARRAY_SIZE(formats_win_lite),
+
+ .enable = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x7, 4),
+ .rb_swap = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 12),
+ .dsp_info = VOP_REG(RK3308_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
+ .dsp_st = VOP_REG(RK3308_LIT_WIN1_DSP_ST, 0xffffffff, 0),
+ .yrgb_mst = VOP_REG(RK3308_LIT_WIN1_MST, 0xffffffff, 0),
+ .yrgb_vir = VOP_REG(RK3308_LIT_WIN1_VIR, 0x1fff, 0),
+
+ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 2),
+ .alpha_mode = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
+ .alpha_en = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
+};
+
+static const struct vop_win_data rk3308_vop_lit_win_data[] = {
+ { .base = 0x00, .phy = &rk3308_lit_win0_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+ { .base = 0x00, .phy = &rk3308_lit_win1_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_modeset rk3308_modeset = {
+ .htotal_pw = VOP_REG(RK3308_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
+ .hact_st_end = VOP_REG(RK3308_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
+ .vtotal_pw = VOP_REG(RK3308_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
+ .vact_st_end = VOP_REG(RK3308_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
+};
+
+static const struct vop_data rk3308_vop = {
+ .version = VOP_VERSION(2, 7),
+ .output = &rk3308_ctrl_data,
+ .common = &rk3308_common,
+ .modeset = &rk3308_modeset,
+ .intr = &rk3308_lit_intr,
+ .win = rk3308_vop_lit_win_data,
+ .win_size = ARRAY_SIZE(rk3308_vop_lit_win_data),
+ .feature = VOP_FEATURE_INTERNAL_RGB,
+ .max_output = { 1280, 800 },
+};
+
static const struct vop_common rv1126_common = {
.standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
.out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
@@ -1254,6 +1354,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
.data = &rk3188_vop },
{ .compatible = "rockchip,rk3288-vop",
.data = &rk3288_vop },
+ { .compatible = "rockchip,rk3308-vop",
+ .data = &rk3308_vop },
{ .compatible = "rockchip,rk3368-vop",
.data = &rk3368_vop },
{ .compatible = "rockchip,rk3366-vop",
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -1033,4 +1033,64 @@
#define RK3066_DSP_LUT_ADDR 0x800
/* rk3066 register definition end */
+/* rk3308 register definition */
+#define RK3308_LIT_REG_CFG_DONE 0x00000
+#define RK3308_LIT_VERSION 0x00004
+#define RK3308_LIT_DSP_BG 0x00008
+#define RK3308_LIT_MCU_CTRL 0x0000c
+#define RK3308_LIT_SYS_CTRL0 0x00010
+#define RK3308_LIT_SYS_CTRL1 0x00014
+#define RK3308_LIT_SYS_CTRL2 0x00018
+#define RK3308_LIT_DSP_CTRL0 0x00020
+#define RK3308_LIT_DSP_CTRL2 0x00028
+#define RK3308_LIT_VOP_STATUS 0x0002c
+#define RK3308_LIT_LINE_FLAG 0x00030
+#define RK3308_LIT_INTR_EN 0x00034
+#define RK3308_LIT_INTR_CLEAR 0x00038
+#define RK3308_LIT_INTR_STATUS 0x0003c
+#define RK3308_LIT_WIN0_CTRL0 0x00050
+#define RK3308_LIT_WIN0_CTRL1 0x00054
+#define RK3308_LIT_WIN0_COLOR_KEY 0x00058
+#define RK3308_LIT_WIN0_VIR 0x0005c
+#define RK3308_LIT_WIN0_YRGB_MST0 0x00060
+#define RK3308_LIT_WIN0_CBR_MST0 0x00064
+#define RK3308_LIT_WIN0_ACT_INFO 0x00068
+#define RK3308_LIT_WIN0_DSP_INFO 0x0006c
+#define RK3308_LIT_WIN0_DSP_ST 0x00070
+#define RK3308_LIT_WIN0_SCL_FACTOR_YRGB 0x00074
+#define RK3308_LIT_WIN0_SCL_FACTOR_CBR 0x00078
+#define RK3308_LIT_WIN0_SCL_OFFSET 0x0007c
+#define RK3308_LIT_WIN0_ALPHA_CTRL 0x00080
+#define RK3308_LIT_WIN1_CTRL0 0x00090
+#define RK3308_LIT_WIN1_CTRL1 0x00094
+#define RK3308_LIT_WIN1_VIR 0x00098
+#define RK3308_LIT_WIN1_MST 0x000a0
+#define RK3308_LIT_WIN1_DSP_INFO 0x000a4
+#define RK3308_LIT_WIN1_DSP_ST 0x000a8
+#define RK3308_LIT_WIN1_COLOR_KEY 0x000ac
+#define RK3308_LIT_WIN1_ALPHA_CTRL 0x000bc
+#define RK3308_LIT_DSP_HTOTAL_HS_END 0x00100
+#define RK3308_LIT_DSP_HACT_ST_END 0x00104
+#define RK3308_LIT_DSP_VTOTAL_VS_END 0x00108
+#define RK3308_LIT_DSP_VACT_ST_END 0x0010c
+#define RK3308_LIT_DSP_VS_ST_END_F1 0x00110
+#define RK3308_LIT_DSP_VACT_ST_END_F1 0x00114
+#define RK3308_LIT_BCSH_CTRL 0x00160
+#define RK3308_LIT_BCSH_COL_BAR 0x00164
+#define RK3308_LIT_BCSH_BCS 0x00168
+#define RK3308_LIT_BCSH_H 0x0016c
+#define RK3308_LIT_FRC_LOWER01_0 0x00170
+#define RK3308_LIT_FRC_LOWER01_1 0x00174
+#define RK3308_LIT_FRC_LOWER10_0 0x00178
+#define RK3308_LIT_FRC_LOWER10_1 0x0017c
+#define RK3308_LIT_FRC_LOWER11_0 0x00180
+#define RK3308_LIT_FRC_LOWER11_1 0x00184
+#define RK3308_LIT_MCU_RW_BYPASS_PORT 0x0018c
+#define RK3308_LIT_DBG_REG_000 0x00190
+#define RK3308_LIT_BLANKING_VALUE 0x001f4
+#define RK3308_LIT_FLAG_REG_FRM_VALID 0x001f8
+#define RK3308_LIT_FLAG_REG 0x001fc
+#define RK3308_LIT_GAMMA_LUT_ADDR 0x00a00
+/* rk3308 register definition end */
+
#endif /* _ROCKCHIP_VOP_REG_H */
--
Armbian
Reference in New Issue View Git Blame Copy Permalink