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* Bump meson64 edge from 6.7 to 6.8 Changes to be committed: modified: config/sources/families/include/meson64_common.inc renamed: patch/kernel/archive/meson64-6.7 -> patch/kernel/archive/meson64-6.8 modified: patch/kernel/archive/meson64-6.8/board-bananapi-cm4-cm4io-fixes.patch modified: patch/kernel/archive/meson64-6.8/general-input-touchscreen-Add-D-WAV-Multitouch.patch new file: patch/kernel/archive/meson64-6.8/kernel-6.8-tools-cgroup-makefile.patch * updates from rewrite-kernel-patches * updates from rewrite-kernel-config
52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Vyacheslav Bocharov <adeep@lexina.in>
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Date: Thu, 10 Nov 2022 14:52:47 +0300
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Subject: arm64: dts: docs: Update mmc meson-gx documentation for new config
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option amlogic,mmc-phase
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- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
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clock with values:
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0: CLK_PHASE_0 - 0 phase
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1: CLK_PHASE_90 - 90 phase
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2: CLK_PHASE_180 - 180 phase
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3: CLK_PHASE_270 - 270 phase
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By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
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Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
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- rpardini: in 6.4, Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt is gone
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and now replaced by Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
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---
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Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml | 11 ++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
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index bc403ae9e5d9..176c8854f613 100644
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--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
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+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
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@@ -51,6 +51,16 @@ properties:
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set when controller's internal DMA engine cannot access the DRAM memory,
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like on the G12A dedicated SDIO controller.
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+ amlogic,mmc-phases:
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+ type: integer
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+ description: |
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+ 3-element array of clock phases for core, tx, rx clock with values:
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+ 0: CLK_PHASE_0 - 0 phase
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+ 1: CLK_PHASE_90 - 90 phase
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+ 2: CLK_PHASE_180 - 180 phase
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+ 3: CLK_PHASE_270 - 270 phase
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+ By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
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+
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required:
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- compatible
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- reg
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@@ -73,4 +83,5 @@ examples:
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clock-names = "core", "clkin0", "clkin1";
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pinctrl-0 = <&emm_pins>;
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resets = <&reset_mmc>;
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+ amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
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};
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--
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Armbian
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