diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index e4a5857c1..9bbba9809 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -26,7 +26,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clocks = <&clock CLK_KFC_CLK>;
-			clock-frequency = <1000000000>;
+			clock-frequency = <1500000000>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -38,7 +38,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clocks = <&clock CLK_KFC_CLK>;
-			clock-frequency = <1000000000>;
+			clock-frequency = <1500000000>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -50,7 +50,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clocks = <&clock CLK_KFC_CLK>;
-			clock-frequency = <1000000000>;
+			clock-frequency = <1500000000>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -62,7 +62,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clocks = <&clock CLK_KFC_CLK>;
-			clock-frequency = <1000000000>;
+			clock-frequency = <1500000000>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -74,7 +74,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 			clocks = <&clock CLK_ARM_CLK>;
-			clock-frequency = <1800000000>;
+			clock-frequency = <2000000000>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -86,7 +86,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 			clocks = <&clock CLK_ARM_CLK>;
-			clock-frequency = <1800000000>;
+			clock-frequency = <2000000000>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -98,7 +98,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x2>;
 			clocks = <&clock CLK_ARM_CLK>;
-			clock-frequency = <1800000000>;
+			clock-frequency = <2000000000>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -110,7 +110,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x3>;
 			clocks = <&clock CLK_ARM_CLK>;
-			clock-frequency = <1800000000>;
+			clock-frequency = <2000000000>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319f..5e6b55094 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -21,6 +21,19 @@
 };
 
 &cluster_a15_opp_table {
+	opp-2000000000 {
+		opp-hz = /bits/ 64 <2000000000>;
+		opp-microvolt = <1312500>;
+		clock-latency-ns = <140000>;
+	};
+	opp-1900000000 {
+		opp-hz = /bits/64 <1900000000>;
+		opp-microvolt = <1250000>;
+		clock-latency-ns = <140000>;
+	};
+	opp-1800000000 {
+		opp-microvolt = <1200000>;
+	};
 	opp-1700000000 {
 		opp-microvolt = <1250000>;
 	};
@@ -82,8 +95,20 @@
 };
 
 &cluster_a7_opp_table {
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1250000>;
+		clock-latency-ns = <140000>;
+	};
+	opp-1400000000 {
+		opp-hz = /bits/ 64 <1400000000>;
+		opp-microvolt = <1250000>;
+		clock-latency-ns = <140000>;
+	};
 	opp-1300000000 {
+		opp-hz = /bits/ 64 <1300000000>;
 		opp-microvolt = <1250000>;
+		clock-latency-ns = <140000>;
 	};
 	opp-1200000000 {
 		opp-microvolt = <1250000>;
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 95e1bf694..04f049832 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1398,6 +1398,8 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
 		 ((cpud) << 4)))
 
 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
 	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
 	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
 	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
@@ -1445,6 +1447,7 @@ static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
 		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
 
 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1500000, E5420_KFC_DIV(3, 5, 3), },
 	{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
 	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index f53fb41ef..04215e3c3 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1229,6 +1229,15 @@ static int cpufreq_online(unsigned int cpu)
 	cpumask_and(policy->cpus, policy->cpus, cpu_online_mask);
 
 	if (new_policy) {
+
+		if (cpumask_test_cpu(0, policy->cpus)) {
+			policy->min = 200000;
+			policy->max = 1500000;
+		} else {
+			policy->min = 200000;
+			policy->max = 2000000;
+		}
+
 		policy->user_policy.min = policy->min;
 		policy->user_policy.max = policy->max;