From 997c2fe858ecc56b1d0d2ccd56cce6c571b87d17 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 13:50:48 +0100 Subject: [PATCH 59/96] ARM: dts: meson: add the VPU - WiP WiP Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/amlogic/meson.dtsi | 10 +++ arch/arm/boot/dts/amlogic/meson8.dtsi | 80 ++++++++++++++++++++++++ arch/arm/boot/dts/amlogic/meson8b.dtsi | 81 +++++++++++++++++++++++++ arch/arm/boot/dts/amlogic/meson8m2.dtsi | 4 ++ 4 files changed, 175 insertions(+) diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index d7f50fec8..d729a06da 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -38,6 +38,16 @@ hhi: system-controller@4000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x400>; + + + cvbs_dac: video-dac@2f4 { + compatible = "amlogic,meson-cvbs-dac"; + reg = <0x2f4 0x8>; + + #phy-cells = <0>; + + status = "disabled"; + }; }; aiu: audio-controller@5400 { diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 454c35530..519443e19 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -314,6 +314,71 @@ mali: gpu@c0000 { operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; + + vpu: vpu@100000 { + compatible = "amlogic,meson8-vpu"; + + reg = <0x100000 0x10000>; + reg-names = "vpu"; + + interrupts = ; + + amlogic,canvas = <&canvas>; + + /* + * The VCLK{,2}_IN path always needs to derived from + * the CLKID_VID_PLL_FINAL_DIV so other clocks like + * MPLL1 are not used (MPLL1 is reserved for audio + * purposes). + */ + assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, + <&clkc CLKID_VCLK2_IN_SEL>; + assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, + <&clkc CLKID_VID_PLL_FINAL_DIV>; + + clocks = <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_HDMI_INTR_SYNC>, + <&clkc CLKID_GCLK_VENCI_INT>, + <&clkc CLKID_HDMI_PLL_HDMI_OUT>, + <&clkc CLKID_HDMI_TX_PIXEL>, + <&clkc CLKID_CTS_ENCP>, + <&clkc CLKID_CTS_ENCI>, + <&clkc CLKID_CTS_ENCT>, + <&clkc CLKID_CTS_ENCL>, + <&clkc CLKID_CTS_VDAC0>; + clock-names = "vpu_intr", + "hdmi_intr_sync", + "venci_int", + "tmds", + "hdmi_tx_pixel", + "cts_encp", + "cts_enci", + "cts_enct", + "cts_encl", + "cts_vdac0"; + + resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; + reset-names = "vid_pll_pre", + "vid_pll_post", + "vid_pll_soft_pre", + "vid_pll_soft_post"; + + phys = <&cvbs_dac>; + phy-names = "cvbs-dac"; + + power-domains = <&pwrc PWRC_MESON8_VPU_ID>; + + #address-cells = <1>; + #size-cells = <0>; + + /* CVBS VDAC output port */ + cvbs_vdac_port: port@0 { + reg = <0>; + }; + }; }; }; /* end of / */ @@ -617,6 +682,17 @@ smp-sram@1ff80 { }; }; +&cvbs_dac { + compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; + + clocks = <&clkc CLKID_CTS_VDAC0>; + + nvmem-cells = <&cvbs_trimming>; + nvmem-cell-names = "cvbs_trimming"; + + status = "okay"; +}; + &efuse { compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; @@ -626,6 +702,10 @@ temperature_calib: calib@1f4 { /* only the upper two bytes are relevant */ reg = <0x1f4 0x4>; }; + + cvbs_trimming: calib@1f8 { + reg = <0x1f8 0x2>; + }; }; ðmac { diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 5ffedca99..87aa74675 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -276,6 +276,71 @@ mali: gpu@c0000 { operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; + + vpu: vpu@100000 { + compatible = "amlogic,meson8b-vpu"; + + reg = <0x100000 0x10000>; + reg-names = "vpu"; + + interrupts = ; + + amlogic,canvas = <&canvas>; + + /* + * The VCLK{,2}_IN path always needs to derived from + * the CLKID_VID_PLL_FINAL_DIV so other clocks like + * MPLL1 are not used (MPLL1 is reserved for audio + * purposes). + */ + assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, + <&clkc CLKID_VCLK2_IN_SEL>; + assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, + <&clkc CLKID_VID_PLL_FINAL_DIV>; + + clocks = <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_HDMI_INTR_SYNC>, + <&clkc CLKID_GCLK_VENCI_INT>, + <&clkc CLKID_HDMI_PLL_HDMI_OUT>, + <&clkc CLKID_HDMI_TX_PIXEL>, + <&clkc CLKID_CTS_ENCP>, + <&clkc CLKID_CTS_ENCI>, + <&clkc CLKID_CTS_ENCT>, + <&clkc CLKID_CTS_ENCL>, + <&clkc CLKID_CTS_VDAC0>; + clock-names = "vpu_intr", + "hdmi_intr_sync", + "venci_int", + "tmds", + "hdmi_tx_pixel", + "cts_encp", + "cts_enci", + "cts_enct", + "cts_encl", + "cts_vdac0"; + + resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, + <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; + reset-names = "vid_pll_pre", + "vid_pll_post", + "vid_pll_soft_pre", + "vid_pll_soft_post"; + + phys = <&cvbs_dac>; + phy-names = "cvbs-dac"; + + power-domains = <&pwrc PWRC_MESON8_VPU_ID>; + + #address-cells = <1>; + #size-cells = <0>; + + /* CVBS VDAC output port */ + cvbs_vdac_port: port@0 { + reg = <0>; + }; + }; }; }; /* end of / */ @@ -389,6 +454,8 @@ &ao_arc_rproc { sram = <&ao_arc_sram>; resets = <&reset RESET_MEDIA_CPU>; clocks = <&clkc CLKID_AO_MEDIA_CPU>; + status = "okay"; + firmware-name = "zephyr.elf"; }; &cbus { @@ -547,6 +614,16 @@ smp-sram@1ff80 { }; }; +&cvbs_dac { + compatible = "amlogic,meson8b-cvbs-dac", "amlogic,meson-cvbs-dac"; + + clocks = <&clkc CLKID_CTS_VDAC0>; + + nvmem-cells = <&cvbs_trimming>; + nvmem-cell-names = "cvbs_trimming"; + + status = "okay"; +}; &efuse { compatible = "amlogic,meson8b-efuse"; @@ -557,6 +634,10 @@ temperature_calib: calib@1f4 { /* only the upper two bytes are relevant */ reg = <0x1f4 0x4>; }; + + cvbs_trimming: calib@1f8 { + reg = <0x1f8 0x2>; + }; }; ðmac { diff --git a/arch/arm/boot/dts/amlogic/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi index 6725dd9fd..fcb2ad976 100644 --- a/arch/arm/boot/dts/amlogic/meson8m2.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8m2.dtsi @@ -96,6 +96,10 @@ &usb1_phy { compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; }; +&vpu { + compatible = "amlogic,meson8m2-vpu"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; -- 2.45.1