diff -Nur a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c	2016-02-15 22:44:30.000000000 +0100
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c	2016-03-07 22:29:38.603830589 +0100
@@ -42,6 +42,9 @@
 
 	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
 	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+	
+	/* enable R_PIO and de-assert resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO);
 }
 #endif
 
diff -Nur a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
--- a/arch/arm/dts/sun8i-h3.dtsi	2016-02-15 22:44:30.000000000 +0100
+++ b/arch/arm/dts/sun8i-h3.dtsi	2016-03-07 22:27:45.575183986 +0100
@@ -285,6 +285,25 @@
 			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 			clock-output-names = "mbus";
 		};
+
+		apb0: apb0_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk@01f01428 {
+			compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <1>;
+			clock-output-names = "apb0_pio", "apb0_ir";
+		};
 	};
 
 	soc {
@@ -591,5 +610,23 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_reset: reset@01f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		r_pio: pinctrl@01f02c00 {
+			compatible = "allwinner,sun8i-h3-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_reset 0>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
 	};
 };
diff -Nur a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
--- a/drivers/gpio/sunxi_gpio.c	2016-03-07 22:19:30.000000000 +0100
+++ b/drivers/gpio/sunxi_gpio.c	2016-03-07 22:24:28.194532112 +0100
@@ -276,8 +276,10 @@
 				"allwinner,sun6i-a31-r-pinctrl") == 0) {
 		start = 'L' - 'A';
 		no_banks = 2; /* L & M */
-	} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-a23-r-pinctrl") == 0) {
+	} else if ((fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+				"allwinner,sun8i-a23-r-pinctrl") == 0) ||
+				(fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+				"allwinner,sun8i-h3-r-pinctrl") == 0)) {
 		start = 'L' - 'A';
 		no_banks = 1; /* L only */
 	} else {
@@ -320,6 +322,7 @@
 	{ .compatible = "allwinner,sun9i-a80-pinctrl" },
 	{ .compatible = "allwinner,sun6i-a31-r-pinctrl" },
 	{ .compatible = "allwinner,sun8i-a23-r-pinctrl" },
+	{ .compatible = "allwinner,sun8i-h3-r-pinctrl" },
 	{ }
 };