From 83dd3e784cf7a6f7e5271740e01dd0dd98b3d618 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 19 Feb 2025 11:20:08 +0300 Subject: [PATCH] arm64: dts: Add BananaPi M4 Berry support --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h618-bananapi-m4-berry.dts | 480 ++++++++++++++++++ 2 files changed, 481 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 3f0bb0aae3ff..394cded5e038 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-cherryba-m1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-berry.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts new file mode 100644 index 000000000000..0cd6c6d83a4b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" +/* #include "axp313a.dtsi" */ + +#include +#include +#include +#include + +/ { + model = "BananaPi M4 Berry"; + compatible = "BiPai,bananapi-m4berry", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + ethernet1 = &emac1; + serial0 = &uart0; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-sw3 { + label = "sw3"; + linux,code = ; + gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + linux,default-trigger = "heartbeat"; + }; + }; + + wifi_usb { + compatible = "usb-wifi"; + status = "okay"; + power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */ + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; + + reg_vcc3v3: vcc3v3 { + /* SY8089 DC/DC converter */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + regulator-always-on; + }; + + reg_vcc_wifi_io: vcc-wifi-io { + /* Always on 1.8V/300mA regulator for WiFi and BT IO */ + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_vcc3v3>; + }; + + ac200_pwm_clk: ac200_clk { + compatible = "pwm-clock"; + #clock-cells = <0>; + // pwm5 period_ns = 500 > 334 for select 24M clock. + pwms = <&pwm 5 500 0>; + clock-frequency = <2000000>; + status = "okay"; + }; + + soc { + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h616-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + pwm-number = <6>; + pwm-base = <0x0>; + sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>; + #pwm-cells = <3>; + status = "okay"; + }; + + pwm0: pwm0@0300a000 { + compatible = "allwinner,sunxi-pwm0"; + reg = <0x0 0x0300a010 0x0 0x4>; + reg_base = <0x0300a000>; + }; + + pwm1: pwm1@0300a000 { + compatible = "allwinner,sunxi-pwm1"; + reg = <0x0 0x0300a010 0x0 0x4>; + reg_base = <0x0300a000>; + }; + + pwm2: pwm2@0300a000 { + compatible = "allwinner,sunxi-pwm2"; + reg = <0x0 0x0300a012 0x0 0x4>; + reg_base = <0x0300a000>; + }; + + pwm3: pwm3@0300a000 { + compatible = "allwinner,sunxi-pwm3"; + reg = <0x0 0x0300a013 0x0 0x4>; + reg_base = <0x0300a000>; + }; + + pwm4: pwm4@0300a000 { + compatible = "allwinner,sunxi-pwm4"; + reg = <0x0 0x0300a013 0x0 0x4>; + reg_base = <0x0300a000>; + }; + + pwm5: pwm5@0300a000 { + compatible = "allwinner,sunxi-pwm5"; + reg = <0x0 0x0300a015 0x0 0x4>; + reg_base = <0x0300a000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + clk_bypass_output = <0x1>; + }; + }; +}; + +&de { + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_aldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&gpu { + mali-supply = <®_dcdc1>; + status = "disabled"; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "disabled"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&emac1 { + phy-mode = "rmii"; + phy-handle = <&rmii_phy>; + phy-supply = <®_dldo1>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "disabled"; +}; + +&mdio1 { + rmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + pinctrl-0 = <&r_i2c_pins>; + pinctrl-names = "default"; + status = "okay"; + + axp313a: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + wakeup-source; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators{ + reg_dcdc1: dcdc1 { + regulator-name = "dcdc1-gpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "dcdc2-cpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-ramp-delay = <200>; + regulator-always-on; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "dcdc3-dram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_aldo1: aldo1 { + regulator-name = "aldo1-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dldo1: dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; + +&ehci0 { + status = "disabled"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ohci0 { + status = "disabled"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx_pin>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pa_pins>; + + ac200_x: mfd@10 { + compatible = "x-powers,ac200-sunxi"; + reg = <0x10>; + clocks = <&ac200_pwm_clk>; + // ephy id + nvmem-cells = <&ephy_calibration>; + nvmem-cell-names = "calibration"; + + ac200_ephy: phy { + compatible = "x-powers,ac200-ephy-sunxi"; + status = "okay"; + }; + }; +}; + +&i2c4 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; + + spidev@1 { + compatible = "rohm,dh2228fv"; + status = "okay"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT"; + status = "okay"; +}; + +&ahub_dam_plat { + status = "okay"; +}; +/* +&ahub_dam_mach { + status = "okay"; +}; +*/ +&ahub1_plat { + status = "okay"; +}; + +&ahub1_mach { + status = "okay"; +}; +/* +&ahub_i2s2 { + status = "okay"; +}; +*/ +&cpu0 { + cpu-supply = <®_dcdc2>; + status = "okay"; +}; + +&sid { + ephy_calibration: ephy-calibration@2c { + reg = <0x2c 0x2>; + }; +}; -- 2.35.3