new values are based on stabilityTester results
when using 930mV for 1.6GHz and 980mV for 1.8GHz, xhpl failed randomly.
So 930/980mV are the critical operation voltage.Then increase 10mV and
run 100 times test, result shows that xhpl (not always) failed 1~2 times.
It seems +10mV is still not enough to ensure dc-dc output voltage always
above operation voltage, that means the design of dc-dc converter is not
good enough that results in large ripple.
The testing script is "github.com/mzhboy/StabilityTester"
The following configuration have been tested.
1.08-1.32-1.48-1.64-1.8 GHz
900-910-920-930-990 *ok, 930 failed 2/100
900-900-910-940-990 *ok, 990 failed 1/100
890-900-910-940-990 *ok, 990 failed 1/100
880-880-910-940-1000 *ok, 940 failed 2/100
880-880-910-950-1000 *ok, 1000 failed 1/100
880-880-910-950-1010 *ok
use more powerfull 'cpuburn-a53' to do pressure test.
power meter shows that 'cpuburn-a53' consumes much more power than
'stress -c 4' in the same condition. 930mV is not enough when running
'cpuburn-a53' meanwhile 950mV is the minimum voltage.
When running 'cpuburn-a53' at 1.8G, h6 consumes lots of power and generate
such amount of heat that an active cooling is necessary otherwise h6
gets overheat and system crashes. Even with active cooling and heatsink
is in low temperature the junction temperature is still quit high that
it reaches about 88~90 ℃ . Maybe the high thermal resistance of plastic
package causes the problem.
* [sunxi-dev][h6]update orangepi lite2 dts file patch
* [sunxi-dev][h6]update patch for sun50i-h6.dtsi
* [sunxi-dev][h6] new operation voltage table of allwinner h6
The correct operation voltages are find out after many reboots and test (over 20+).
the original 1.16v@1.64/1.8GHz was too high since standard cell voltage
of 28nm@HPC is 0.9v, h6 got overheat very quickly over 110 Celsius and then system hangs,
a power-cycle off is needed to reset soc.
I use 'stress -c 4' to do pressure test, with a medium size passive heatsink on top of h6.
The pressure test proves that the soc has about 4 watt power consuming
that is much lesser than original 6~7.x watt when running at 1.8GHz(orangepi lite2 with
usb Ethernet rtl8153 and usb hub, wifi is connected but not used).
Soc runs much more stable and does not get overheat easily under heavy load
with new opp table.
* [sunxi-dev][h6] orangepi lite2 wifi fix
bcm43455-fmac is buggy, reset to bcm4329-fmac
Add patch to bring A64 pinctrl driver inline with other sunxi pintctrl drivers by disabling strict mode.
With kernel 4.15.y (and later):
* Strict mode was enabled by default via commit 1396007286b1e2fd5dd10ae6a5ccaaaed51ab762 which can/will cause breakage with existing implementations.
* The ability to configure strict mode was added via commit aae842a3ff3385f27f1df8a9ee1494a416ec032d to allow older drivers to maintain existing behavior and avoid breakage.
* Commit cd70387f892205bcd7b8093b0837269b0739cbe0 had then explicitly disabled strict mode for most other existing SoCs but did not include A64.
This change is to update the A64 pinctrl driver similar to the other pre-existing SoC pinctrl drivers.
See 63f8f3badf799c8b63ff33a489886bc138ce5d09 drm: bridge: Constify mode arguments to bridge .mode_set() operation
and fcd70cd36b9bf697122538c9e38e8cf954b2342b drm: Split out drm_probe_helper.h
arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts:12.13-17.6:
Warning (spi_bus_reg): /fragment@0/__overlay__/spiflash: SPI bus unit
address format error, expected "0"
arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts:26.13-31.6:
Warning (spi_bus_reg): /fragment@1/__overlay__/spiflash: SPI bus unit
address format error, expected "0"
Updated DT patch for allwinner unstable timer
Replace previous patch for DT timer node with new patch from upstream commit.
This matches the upstream change to the actual workaround in drivers/clocksource/arm_arch_timer.c
via commit c950ca8c35eeb32224a63adc47e12f9e226da241
