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rockchip64/edge 6.6.y: manually fix 2 patches

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This commit is contained in:
Ricardo Pardini 2023-10-02 15:19:01 +02:00 committed by Igor
parent 21ff27f9f1
commit b51a4537da
2 changed files with 17 additions and 20 deletions
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10
patch/kernel/archive/rockchip64-6.6/general-add-pll-hdmi-timings.patch
View File

@ -69,13 +69,13 @@ Subject: [ARCHEOLOGY] Adding pll hdmi timing to rockchip64-dev too
1 file changed, 71 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index fbdc23953b52..a67213a20d9c 100644
index 053bd62e31ba..db774d97918f 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -316,6 +316,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
{594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
{593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
{594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
@@ -464,6 +464,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
{594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0},
{594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0},
{594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0},
+ { 25175000, 25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 31500000, 31500000, 1, 21, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 33750000, 33750000, 1, 45, 1, 2, 2, 1, 2, 3, 4, 0, 0},

27
patch/kernel/archive/rockchip64-6.6/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
View File

@ -74,10 +74,10 @@ Subject: [ARCHEOLOGY] rockchip-[current,edge]: add pcie hack and lsi scsi/sas
4 files changed, 41 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 23ebe34ff901..9cfdac82e52c 100644
index 0a1731a0f0ef..a47b48a8aaec 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4469,6 +4469,14 @@
@@ -4485,6 +4485,14 @@
nomsi Do not use MSI for native PCIe PME signaling (this makes
all PCIe root ports use INTx for all services).
@ -93,18 +93,15 @@ index 23ebe34ff901..9cfdac82e52c 100644
pd_ignore_unused
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index 2438bc9b3a1a..dc4fbc8914a4 100644
index afbbdccd195d..f7fc4df0cee3 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -24,6 +24,7 @@
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
@@ -32,10 +32,14 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/regmap.h>
+#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_pci.h>
@@ -38,6 +39,9 @@
#include "../pci.h"
#include "pcie-rockchip.h"
@ -114,7 +111,7 @@ index 2438bc9b3a1a..dc4fbc8914a4 100644
static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
{
u32 status;
@@ -932,6 +936,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
@@ -930,6 +934,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct pci_host_bridge *bridge;
int err;
@ -122,7 +119,7 @@ index 2438bc9b3a1a..dc4fbc8914a4 100644
if (!dev->of_node)
return -ENODEV;
@@ -981,6 +986,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
@@ -979,6 +984,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
bridge->sysdata = rockchip;
bridge->ops = &rockchip_pcie_ops;
@ -150,10 +147,10 @@ index 2438bc9b3a1a..dc4fbc8914a4 100644
if (err)
goto err_remove_irq_domain;
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 1aa84035a8bc..c2bf64fcf300 100644
index 0ef2e622d36e..7255c1234fed 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -150,6 +150,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
@@ -151,6 +151,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
return PTR_ERR(rockchip->clk_pcie_pm);
}