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2adcad64dc
pd_alive control cru, grf, timer, gpio and wdt, when turn off logic power rail, these register value will back to reset value, we need to save them value in suspend and restore them when resuem, since timer will reinitial in kernel, so it not need to save/restore. Change-Id: I0fc2a011d3cdc04b66ffbf728e769eb28b51ee38 Signed-off-by: Lin Huang <hl@rock-chips.com>
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_PRIVATE_H__
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#define __PLAT_PRIVATE_H__
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#ifndef __ASSEMBLY__
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#include <mmio.h>
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#include <psci.h>
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#include <stdint.h>
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#include <xlat_tables.h>
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#define __sramdata __attribute__((section(".sram.data")))
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#define __sramconst __attribute__((section(".sram.rodata")))
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#define __sramfunc __attribute__((section(".sram.text")))
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#define __pmusramdata __attribute__((section(".pmusram.data")))
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#define __pmusramconst __attribute__((section(".pmusram.rodata")))
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#define __pmusramfunc __attribute__((section(".pmusram.text")))
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extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
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extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
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extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
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extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
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extern uint32_t __sram_incbin_start, __sram_incbin_end;
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extern uint32_t __sram_incbin_real_end;
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/******************************************************************************
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* The register have write-mask bits, it is mean, if you want to set the bits,
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* you needs set the write-mask bits at the same time,
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* The write-mask bits is in high 16-bits.
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* The fllowing macro definition helps access write-mask bits reg efficient!
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******************************************************************************/
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#define REG_MSK_SHIFT 16
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#ifndef WMSK_BIT
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#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
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#endif
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/* set one bit with write mask */
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#ifndef BIT_WITH_WMSK
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#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
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#endif
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#ifndef BITS_SHIFT
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#define BITS_SHIFT(bits, shift) (bits << (shift))
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#endif
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#ifndef BITS_WITH_WMASK
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#define BITS_WITH_WMASK(bits, msk, shift)\
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(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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#endif
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/******************************************************************************
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* Function and variable prototypes
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*****************************************************************************/
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void plat_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long,
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unsigned long,
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unsigned long,
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unsigned long);
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void plat_cci_init(void);
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void plat_cci_enable(void);
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void plat_cci_disable(void);
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void plat_delay_timer_init(void);
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void params_early_setup(void *plat_params_from_bl2);
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void plat_rockchip_gic_driver_init(void);
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void plat_rockchip_gic_init(void);
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void plat_rockchip_gic_cpuif_enable(void);
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void plat_rockchip_gic_cpuif_disable(void);
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void plat_rockchip_gic_pcpu_init(void);
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void plat_rockchip_pmu_init(void);
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void plat_rockchip_soc_init(void);
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uintptr_t plat_get_sec_entrypoint(void);
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void platform_cpu_warmboot(void);
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struct gpio_info *plat_get_rockchip_gpio_reset(void);
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struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
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struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
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struct apio_info *plat_get_rockchip_suspend_apio(void);
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void plat_rockchip_gpio_init(void);
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void plat_rockchip_save_gpio(void);
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void plat_rockchip_restore_gpio(void);
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_off(void);
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int rockchip_soc_sys_pwr_dm_suspend(void);
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int rockchip_soc_cores_pwr_dm_suspend(void);
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int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_on_finish(void);
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int rockchip_soc_sys_pwr_dm_resume(void);
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int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_resume(void);
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void __dead2 rockchip_soc_soft_reset(void);
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void __dead2 rockchip_soc_system_off(void);
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void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
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const psci_power_state_t *target_state);
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void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
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extern const unsigned char rockchip_power_domain_tree_desc[];
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extern void *pmu_cpuson_entrypoint;
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extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
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extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
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extern const mmap_region_t plat_rk_mmap[];
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void rockchip_plat_mmu_el3(void);
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#endif /* __ASSEMBLY__ */
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/******************************************************************************
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* cpu up status
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* The bits of macro value is not more than 12 bits for cmp instruction!
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******************************************************************************/
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#define PMU_CPU_HOTPLUG 0xf00
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#define PMU_CPU_AUTO_PWRDN 0xf0
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#define PMU_CLST_RET 0xa5
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#endif /* __PLAT_PRIVATE_H__ */
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