arm-trusted-firmware/plat/qemu/aarch32/plat_helpers.S
Etienne Carriere 765ed9fc55 qemu: support ARMv7/Cortex-A15
Define Qemu AArch32 implementation for some platform functions
(core position, secondary boot cores, crash console). These are
derived from the AArch64 implementation.

BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is
the first executable image after BL2.

Support SP_MIN and OP-TEE as BL32: create a sp_min make script target
in Qemu, define mapping for IMAGE_BL32

Minor fix Qemu return value type for plat_get_ns_image_entrypoint().

Qemu model for the Cortex-A15 does not support the virtualization
extension although the core expects it. To overcome the issue, Qemu
ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0.

Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform
used by the Qemu platform.

Qemu Cortex-A15 model integrates a single cluster with up to 4 cores.

Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2018-02-05 10:42:47 +01:00

120 lines
3.0 KiB
ArmAsm

/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <platform_def.h>
.globl plat_my_core_pos
.globl plat_get_my_entrypoint
.globl platform_mem_init
.globl plat_qemu_calc_core_pos
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_secondary_cold_boot_setup
.globl plat_get_my_entrypoint
.globl plat_is_my_cpu_primary
func plat_my_core_pos
ldcopr r0, MPIDR
b plat_qemu_calc_core_pos
endfunc plat_my_core_pos
/*
* unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
* With this function: CorePos = (ClusterId * 4) + CoreId
*/
func plat_qemu_calc_core_pos
and r1, r0, #MPIDR_CPU_MASK
and r0, r0, #MPIDR_CLUSTER_MASK
add r0, r1, r0, LSR #6
bx lr
endfunc plat_qemu_calc_core_pos
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu.
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
ldcopr r0, MPIDR
ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
and r0, r1
cmp r0, #QEMU_PRIMARY_CPU
moveq r0, #1
movne r0, #0
bx lr
endfunc plat_is_my_cpu_primary
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
/* Calculate address of our hold entry */
bl plat_my_core_pos
lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
mov_imm r2, PLAT_QEMU_HOLD_BASE
/* Wait until we have a go */
poll_mailbox:
ldr r1, [r2, r0]
cmp r1, #0
beq 1f
mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
ldr r1, [r0]
bx r1
1:
wfe
b poll_mailbox
endfunc plat_secondary_cold_boot_setup
func plat_get_my_entrypoint
/* TODO support warm boot */
mov r0, #0
bx lr
endfunc plat_get_my_entrypoint
func platform_mem_init
bx lr
endfunc platform_mem_init
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
b console_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(int c)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm r1, PLAT_QEMU_CRASH_UART_BASE
b console_core_putc
endfunc plat_crash_console_putc