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https://github.com/ARM-software/arm-trusted-firmware.git
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ee1ebbd18e
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
239 lines
6.2 KiB
C
239 lines
6.2 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <flowctrl.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <pmc.h>
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#include <psci.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16).
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*/
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#define CPU_CMPLX_RESET_CLR 0x454
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#define CPU_CORE_RESET_MASK 0x10001
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/* Clock and Reset controller registers for system clock's settings */
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#define SCLK_RATE 0x30
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#define SCLK_BURST_POLICY 0x28
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#define SCLK_BURST_POLICY_DEFAULT 0x10000000
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int state_id = psci_get_pstate_id(power_state);
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_POWERDN:
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/*
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* Core powerdown request only for afflvl 0
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*/
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff;
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break;
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case PSTATE_ID_CLUSTER_IDLE:
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case PSTATE_ID_CLUSTER_POWERDN:
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/*
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* Cluster powerdown/idle request only for afflvl 1
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*/
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
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break;
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case PSTATE_ID_SOC_POWERDN:
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/*
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* System powerdown request only for afflvl 2
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*/
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for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
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PLAT_SYS_SUSPEND_STATE_ID;
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break;
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default:
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ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
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return PSCI_E_INVALID_PARAMS;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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unsigned int ncpu)
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{
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plat_local_state_t target = *states;
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int cpu = plat_my_core_pos();
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int core_pos = read_mpidr() & MPIDR_CPU_MASK;
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/* get the power state at this level */
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if (lvl == MPIDR_AFFLVL1)
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target = *(states + core_pos);
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if (lvl == MPIDR_AFFLVL2)
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target = *(states + cpu);
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/* Cluster idle/power-down */
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if ((lvl == MPIDR_AFFLVL1) && ((target == PSTATE_ID_CLUSTER_IDLE) ||
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(target == PSTATE_ID_CLUSTER_POWERDN))) {
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return target;
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}
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/* System Suspend */
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if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
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(target == PSTATE_ID_SOC_POWERDN))
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return PSTATE_ID_SOC_POWERDN;
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/* default state */
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return PSCI_LOCAL_STATE_RUN;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr();
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
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unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
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unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) ||
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(stateid_afflvl0 == PSTATE_ID_SOC_POWERDN));
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assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) ||
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(stateid_afflvl1 == PSTATE_ID_SOC_POWERDN));
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/* suspend the entire soc */
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tegra_fc_soc_powerdn(mpidr);
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} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) {
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assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_IDLE);
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/* Prepare for cluster idle */
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tegra_fc_cluster_idle(mpidr);
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} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) {
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assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_POWERDN);
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/* Prepare for cluster powerdn */
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tegra_fc_cluster_powerdn(mpidr);
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} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
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/* Prepare for cpu powerdn */
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tegra_fc_cpu_powerdn(mpidr);
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} else {
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ERROR("%s: Unknown state id\n", __func__);
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return PSCI_E_NOT_SUPPORTED;
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint32_t val;
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/*
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* Check if we are exiting from SOC_POWERDN.
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*/
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PLAT_SYS_SUSPEND_STATE_ID) {
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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/*
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* Enable WRAP to INCR burst type conversions for
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* incoming requests on the AXI slave ports.
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*/
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val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG);
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val &= ~ENABLE_UNSUP_TX_ERRORS;
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val |= ENABLE_WRAP_TO_INCR_BURSTS;
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mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val);
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/*
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* Restore Boot and Power Management Processor (BPMP) reset
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* address and reset it.
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*/
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tegra_fc_reset_bpmp();
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}
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/*
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* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
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* used for power management and boot purposes. Inform the BPMP that
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* we have completed the cluster power up.
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*/
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tegra_fc_lock_active_cluster();
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Turn on CPU using flow controller or PMC */
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if (cpu_powergate_mask[cpu] == 0) {
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tegra_pmc_cpu_on(cpu);
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cpu_powergate_mask[cpu] = 1;
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} else {
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_system_reset(void)
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{
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/*
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* Set System Clock (SCLK) to POR default so that the clock source
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* for the PMC APB clock would not be changed due to system reset.
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*/
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
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SCLK_BURST_POLICY_DEFAULT);
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
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/* Wait 1 ms to make sure clock source/device logic is stabilized. */
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mdelay(1);
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return PSCI_E_SUCCESS;
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}
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