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https://github.com/ARM-software/arm-trusted-firmware.git
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ee1ebbd18e
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <denver.h>
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#include <flowctrl.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <pmc.h>
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#include <psci.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16)
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*/
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#define CPU_CMPLX_RESET_CLR 0x344
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#define CPU_CORE_RESET_MASK 0x10001
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/* Clock and Reset controller registers for system clock's settings */
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#define SCLK_RATE 0x30
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#define SCLK_BURST_POLICY 0x28
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#define SCLK_BURST_POLICY_DEFAULT 0x10000000
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int state_id = psci_get_pstate_id(power_state);
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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/*
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* Sanity check the requested state id, power level and CPU number.
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* Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
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* i.e. CPU 0
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*/
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if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
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ERROR("unsupported state id @ power level\n");
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return PSCI_E_INVALID_PARAMS;
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}
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/* Set lower power states to PLAT_MAX_OFF_STATE */
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for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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/* Set the SYSTEM_SUSPEND state-id */
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
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PSTATE_ID_SOC_POWERDN;
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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if (cpu_powergate_mask[cpu] == 0) {
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Power on CPU using PMC */
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tegra_pmc_cpu_on(cpu);
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/* Fill in the CPU powergate mask */
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cpu_powergate_mask[cpu] = 1;
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} else {
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/* Power on CPU using Flow Controller */
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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/* Disable DCO operations */
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denver_disable_dco();
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/* Power down the CPU */
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write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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#if ENABLE_ASSERTIONS
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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/* SYSTEM_SUSPEND only on CPU0 */
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assert(cpu == 0);
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#endif
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/* Allow restarting CPU #1 using PMC on suspend exit */
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cpu_powergate_mask[1] = 0;
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/* Program FC to enter suspend state */
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tegra_fc_cpu_powerdn(read_mpidr());
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/* Disable DCO operations */
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denver_disable_dco();
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/* Program the suspend state ID */
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write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_system_reset(void)
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{
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/*
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* Set System Clock (SCLK) to POR default so that the clock source
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* for the PMC APB clock would not be changed due to system reset.
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*/
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
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SCLK_BURST_POLICY_DEFAULT);
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
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/* Wait 1 ms to make sure clock source/device logic is stabilized. */
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mdelay(1);
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return PSCI_E_SUCCESS;
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}
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