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https://github.com/ARM-software/arm-trusted-firmware.git
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ee1ebbd18e
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <debug.h>
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#include <mmio.h>
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#include <mt_cpuxgpt.h>
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#include <platform.h>
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#include <stdint.h>
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#define CPUXGPT_BASE 0x10200000
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#define INDEX_BASE (CPUXGPT_BASE+0x0674)
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#define CTL_BASE (CPUXGPT_BASE+0x0670)
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uint64_t normal_time_base;
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uint64_t atf_time_base;
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void sched_clock_init(uint64_t normal_base, uint64_t atf_base)
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{
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normal_time_base = normal_base;
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atf_time_base = atf_base;
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}
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uint64_t sched_clock(void)
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{
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uint64_t cval;
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cval = (((read_cntpct_el0() - atf_time_base)*1000)/
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SYS_COUNTER_FREQ_IN_MHZ) + normal_time_base;
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return cval;
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}
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/*
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* Return: 0 - Trying to disable the CPUXGPT control bit,
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* and not allowed to disable it.
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* Return: 1 - reg_addr is not realted to disable the control bit.
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*/
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unsigned char check_cpuxgpt_write_permission(unsigned int reg_addr,
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unsigned int reg_value)
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{
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unsigned int idx;
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unsigned int ctl_val;
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if (reg_addr == CTL_BASE) {
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idx = mmio_read_32(INDEX_BASE);
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/* idx 0: CPUXGPT system control */
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if (idx == 0) {
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ctl_val = mmio_read_32(CTL_BASE);
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if (ctl_val & 1) {
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/*
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* if enable bit already set,
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* then bit 0 is not allow to set as 0
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*/
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if (!(reg_value & 1))
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return 0;
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}
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}
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}
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return 1;
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}
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