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https://github.com/ARM-software/arm-trusted-firmware.git
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33d4af47b0
This patch introduce TF-A support for NXP's ls1043a platform. more details information of ls1043a chip and ls1043ardb board can be found at docs/plat/ls1043a.rst. Boot sequence on ls1043a is: bootrom loads bl1 firstly, then bl1 loads bl2, bl2 will load bl31, bl32 and bl33, bl31 will boot bl32(tee os) and bl33(u-boot or uefi), bl33 boot Linux kernel. Now TF-A on ls1043ardb platform has the following features in this patch: * Support boot from Nor flash. * TF-A can boot bl33 which runs in el2 of non-secure world. * TF-A boot OPTee OS. * Support PSCI Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Chenyin.Ha <Chenyin.Ha@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com> Signed-off-by: Wen He <wen.he_1@nxp.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cci.h>
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#include <debug.h>
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#include <mmio.h>
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#include "plat_ls.h"
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static const int cci_map[] = {
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PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX
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};
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void bl1_platform_setup(void)
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{
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NOTICE(FIRMWARE_WELCOME_STR_LS1043);
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ls_bl1_platform_setup();
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/*
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* Initialize system level generic timer for Layerscape Socs.
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*/
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ls_delay_timer_init();
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/* TODO: remove these DDR code */
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VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
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mmio_write_32(0x1080000 + 0x000, 0x7f000000);
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VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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ls_bl1_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
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/*
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* Enable coherency in Interconnect for the primary CPU's cluster.
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*/
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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}
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unsigned int bl1_plat_get_next_image_id(void)
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{
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return BL2_IMAGE_ID;
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}
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