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127793daba
Support BL31 and PSCI. Enable multiple cores in PSCI. Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __HISI_IPC_H__
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#define __HISI_IPC_H__
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#define HISI_IPC_CORE_ACPU 0x0
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#define HISI_IPC_MCU_INT_SRC_ACPU0_PD 10
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#define HISI_IPC_MCU_INT_SRC_ACPU1_PD 11
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#define HISI_IPC_MCU_INT_SRC_ACPU2_PD 12
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#define HISI_IPC_MCU_INT_SRC_ACPU3_PD 13
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#define HISI_IPC_MCU_INT_SRC_ACPU_PD 16
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#define HISI_IPC_MCU_INT_SRC_ACPU4_PD 26
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#define HISI_IPC_MCU_INT_SRC_ACPU5_PD 27
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#define HISI_IPC_MCU_INT_SRC_ACPU6_PD 28
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#define HISI_IPC_MCU_INT_SRC_ACPU7_PD 29
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#define HISI_IPC_SEM_CPUIDLE 27
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#define HISI_IPC_INT_SRC_NUM 32
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#define HISI_IPC_PM_ON 0
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#define HISI_IPC_PM_OFF 1
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#define HISI_IPC_OK (0)
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#define HISI_IPC_ERROR (-1)
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#define HISI_IPC_BASE_ADDR (0xF7510000)
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#define HISI_IPC_CPU_RAW_INT_ADDR (0xF7510420)
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#define HISI_IPC_ACPU_CTRL(i) (0xF7510800 + (i << 3))
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void hisi_ipc_spin_lock(unsigned int signal);
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void hisi_ipc_spin_unlock(unsigned int signal);
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void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster);
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void hisi_ipc_psci_system_off(void);
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int hisi_ipc_init(void);
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#endif /* __HISI_IPC_H__ */
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