mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-08-15 00:47:02 +02:00
bf4698fdef
This reverts commit 2f18aa1fa3.
It is causing some tests to fail. Until the cause is found and fixed, it
is needed to remove this commit from master.
Change-Id: Ic5ff7a841903a15613e00379e87cbbd8a0e85152
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
160 lines
4.2 KiB
C
160 lines
4.2 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arm_def.h>
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#include <arm_xlat_tables.h>
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#include <bl1.h>
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#include <bl_common.h>
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#include <console.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sp805.h>
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#include <utils.h>
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#include "../../../bl1/bl1_private.h"
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl1_early_platform_setup
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_platform_setup
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#pragma weak bl1_plat_sec_mem_layout
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#pragma weak bl1_plat_prepare_exit
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* BL1 specific platform actions shared between ARM standard platforms.
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******************************************************************************/
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void arm_bl1_early_platform_setup(void)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Enable watchdog */
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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#endif
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/* Initialize the console to provide early debug support */
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console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
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ARM_CONSOLE_BAUDRATE);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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#if !LOAD_IMAGE_V2
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
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bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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BL1_RAM_LIMIT - BL1_RAM_BASE);
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#endif /* LOAD_IMAGE_V2 */
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}
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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*/
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plat_arm_interconnect_enter_coherency();
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup shared between
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* ARM standard platforms. This only does basic initialization. Later
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* architectural setup (bl1_arch_setup()) does not do anything platform
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* specific.
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*****************************************************************************/
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void arm_bl1_plat_arch_setup(void)
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{
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arm_setup_page_tables(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL_CODE_BASE,
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BL1_CODE_END,
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BL1_RO_DATA_BASE,
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BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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#ifdef AARCH32
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enable_mmu_secure(0);
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#else
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enable_mmu_el3(0);
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#endif /* AARCH32 */
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}
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void bl1_plat_arch_setup(void)
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{
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arm_bl1_plat_arch_setup();
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}
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/*
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* Perform the platform specific architecture setup shared between
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* ARM standard platforms.
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*/
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void arm_bl1_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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#if LOAD_IMAGE_V2
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arm_load_tb_fw_config();
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#endif
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}
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void bl1_platform_setup(void)
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{
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arm_bl1_platform_setup();
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}
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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sp805_stop(ARM_SP805_TWDG_BASE);
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#endif
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#ifdef EL3_PAYLOAD_BASE
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/*
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* Program the EL3 payload's entry point address into the CPUs mailbox
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* in order to release secondary CPUs from their holding pen and make
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* them jump there.
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*/
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arm_program_trusted_mailbox(ep_info->pc);
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dsbsy();
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sev();
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#endif
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}
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/*******************************************************************************
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or not.
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******************************************************************************/
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unsigned int bl1_plat_get_next_image_id(void)
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{
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if (!arm_io_is_toc_valid())
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return NS_BL1U_IMAGE_ID;
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return BL2_IMAGE_ID;
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}
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