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86606eb51e
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE defines the platform specific cache line size, it is used to define the size of the cpu data structure CPU_DATA_SIZE aligned on cache line size. Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation of function '_cpu_data_by_index'. Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
48 lines
1.3 KiB
ArmAsm
48 lines
1.3 KiB
ArmAsm
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cpu_data.h>
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.globl init_cpu_data_ptr
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.globl _cpu_data_by_index
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/* -----------------------------------------------------------------
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* void init_cpu_data_ptr(void)
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*
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* Initialise the TPIDR_EL3 register to refer to the cpu_data_t
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* for the calling CPU. This must be called before cm_get_cpu_data()
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*
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* This can be called without a valid stack. It assumes that
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* plat_my_core_pos() does not clobber register x10.
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* clobbers: x0, x1, x10
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* -----------------------------------------------------------------
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*/
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func init_cpu_data_ptr
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mov x10, x30
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bl plat_my_core_pos
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bl _cpu_data_by_index
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msr tpidr_el3, x0
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ret x10
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endfunc init_cpu_data_ptr
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/* -----------------------------------------------------------------
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* cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
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*
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* Return the cpu_data structure for the CPU with given linear index
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*
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* This can be called without a valid stack.
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* clobbers: x0, x1
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* -----------------------------------------------------------------
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*/
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func _cpu_data_by_index
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mov_imm x1, CPU_DATA_SIZE
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mul x0, x0, x1
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adr x1, percpu_data
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add x0, x0, x1
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ret
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endfunc _cpu_data_by_index
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