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e4b34efa18
A per-cpu vbar is installed that implements the workaround by invalidating the branch target buffer (BTB) directly in the case of A9 and A17 and indirectly by invalidating the icache in the case of A15. For Cortex A57 and A72 there is currently no workaround implemented when EL3 is in AArch32 mode so report it as missing. For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are no changes since there is currently no upstream AArch32 EL3 support for these CPUs. Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
112 lines
2.1 KiB
ArmAsm
112 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a9.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a9_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A9_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a9_disable_smp
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func cortex_a9_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A9_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a9_enable_smp
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func check_errata_cve_2017_5715
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#if WORKAROUND_CVE_2017_5715
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2017_5715
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A9. Must follow AAPCS.
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*/
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func cortex_a9_errata_report
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push {r12, lr}
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bl cpu_get_rev_var
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mov r4, r0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
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pop {r12, lr}
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bx lr
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endfunc cortex_a9_errata_report
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#endif
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func cortex_a9_reset_func
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#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
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ldr r0, =workaround_bpiall_runtime_exceptions
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stcopr r0, VBAR
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stcopr r0, MVBAR
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/* isb will be applied in the course of the reset func */
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#endif
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b cortex_a9_enable_smp
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endfunc cortex_a9_reset_func
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func cortex_a9_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a9_disable_smp
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endfunc cortex_a9_core_pwr_dwn
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func cortex_a9_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a9_disable_smp
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endfunc cortex_a9_cluster_pwr_dwn
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declare_cpu_ops cortex_a9, CORTEX_A9_MIDR, \
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cortex_a9_reset_func, \
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cortex_a9_core_pwr_dwn, \
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cortex_a9_cluster_pwr_dwn
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