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e829a3796f
BL31 is running out of space, and the use-case of SPM doesn't require it to be in SRAM. To prevent BL31 from running out of space in the future, move BL31 to DRAM if SPM is enabled. Secure Partition Manager design document updated to reflect the changes. Increased the size of the stack of BL31 for builds with SPM. The translation tables used by SPM in Arm platforms have been moved back to the 'xlat_tables' region instead of 'arm_el3_tzc_dram'. Everything is in DRAM now, so it doesn't make sense to treat them in a different way. Change-Id: Ia6136c8e108b8da9edd90e9d72763dada5e5e5dc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
106 lines
3.4 KiB
C
106 lines
3.4 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ARM_SPM_DEF_H__
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#define __ARM_SPM_DEF_H__
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#include <arm_def.h>
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#include <platform_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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/*
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* If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
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* region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
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* at the base of DRAM.
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*/
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#define ARM_SP_IMAGE_BASE BL32_BASE
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#define ARM_SP_IMAGE_LIMIT BL32_LIMIT
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/* The maximum size of the S-EL0 payload can be 3MB */
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#define ARM_SP_IMAGE_SIZE ULL(0x300000)
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#ifdef IMAGE_BL2
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/* SPM Payload memory. Mapped as RW in BL2. */
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#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#ifdef IMAGE_BL31
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/* SPM Payload memory. Mapped as code in S-EL1 */
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#define ARM_SP_IMAGE_MMAP MAP_REGION2( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_CODE | MT_SECURE | MT_USER, \
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PAGE_SIZE)
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#endif
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/*
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* Memory shared between EL3 and S-EL0. It is used by EL3 to push data into
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* S-EL0, so it is mapped with RW permission from EL3 and with RO permission
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* from S-EL0. Placed after SPM Payload memory.
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*/
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#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE)
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#define PLAT_SPM_BUF_SIZE ULL(0x100000)
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#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RW_DATA | MT_SECURE)
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#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RO_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/*
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* Memory shared between Normal world and S-EL0 for passing data during service
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* requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
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* S-EL0.
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*/
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#define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
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#define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
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#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
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ARM_SP_IMAGE_NS_BUF_BASE, \
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ARM_SP_IMAGE_NS_BUF_BASE, \
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ARM_SP_IMAGE_NS_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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/*
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* RW memory, which uses the remaining Trusted DRAM. Placed after the memory
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* shared between Secure and Non-secure worlds. First there is the stack memory
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* for all CPUs and then there is the common heap memory. Both are mapped with
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* RW permissions.
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*/
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#define PLAT_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
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#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \
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ARM_SP_IMAGE_STACK_TOTAL_SIZE)
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#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE)
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#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \
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PLAT_SP_IMAGE_STACK_BASE, \
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PLAT_SP_IMAGE_STACK_BASE, \
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(ARM_SP_IMAGE_LIMIT - \
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PLAT_SP_IMAGE_STACK_BASE), \
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MT_RW_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/* Total number of memory regions with distinct properties */
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#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
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/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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#endif /* __ARM_SPM_DEF_H__ */
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