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c099cd3942
The patch changes the layout of BL images in memory to enable more efficient use of available space. Previously BL31 was loaded with the expectation that BL2 memory would be reclaimed by BL32 loaded in SRAM. But with increasing memory requirements in the firmware, we can no longer fit BL32 in SRAM anymore which means the BL2 memory is not reclaimed by any runtime image. Positioning BL2 below BL1-RW and above BL31 means that the BL31 NOBITS can be overlaid on BL2 and BL1-RW. This patch also propogates the same memory layout to BL32 for AArch32 mode. The reset addresses for the following configurations are also changed : * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode * When BL2_AT_EL3=1 for BL2 The restriction on BL31 to be only in DRAM when SPM is enabled is now removed with this change. The update to the firmware design guide for the BL memory layout is done in the following patch. Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BOARD_ARM_DEF_H__
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#define __BOARD_ARM_DEF_H__
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#include <v2m_def.h>
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/*
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* Required platform porting definitions common to all ARM
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* development platforms
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*/
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL1)
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#if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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#else
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x200
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#elif defined(IMAGE_BL31)
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#if ENABLE_SPM
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# define PLATFORM_STACK_SIZE 0x500
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#elif PLAT_XLAT_TABLES_DYNAMIC
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# define PLATFORM_STACK_SIZE 0x800
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#else
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# define PLATFORM_STACK_SIZE 0x400
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#endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/*
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* The constants below are not optimised for memory usage. Platforms that wish
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* to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and
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* provide there own values.
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*/
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#if !ARM_BOARD_OPTIMISE_MEM
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*
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* Provide relatively optimised values for the runtime images (BL31 and BL32).
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* Optimisation is less important for the other, transient boot images so a
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* common, maximum value is used across these images.
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*
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* They are also used for the dynamically mapped regions in the images that
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* enable dynamic memory mapping.
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*/
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#if defined(IMAGE_BL31)
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# if ENABLE_SPM
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 7
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# define PLAT_SP_IMAGE_MMAP_REGIONS 7
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x10000
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#endif
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
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#ifdef AARCH32
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/*
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* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
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* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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# define PLAT_ARM_MAX_BL32_SIZE 0x3B000
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*
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* Map mem_protect flash region with read and write permissions
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*/
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#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
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V2M_FLASH_BLOCK_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif /* __BOARD_ARM_DEF_H__ */
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