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f06890ea89
This patch also fixes the assumption that the counters are disabled on the resume path. This is incorrect as the AMU counters are enabled early in the CPU reset function before `cpuamu_context_restore()` runs. Change-Id: I38a94eb166a523f00de18e86860434ffccff2131 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CPUAMU_H__
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#define __CPUAMU_H__
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
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#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
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#define CPUAMCFGR_EL0 S3_3_C15_C10_6
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#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
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/* Activity Monitor Event Counter Registers */
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#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
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#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
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#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
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#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
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#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
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/* Activity Monitor Event Type Registers */
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#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
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#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
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#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
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#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
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#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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uint64_t cpuamu_cnt_read(int idx);
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void cpuamu_cnt_write(int idx, uint64_t val);
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unsigned int cpuamu_read_cpuamcntenset_el0(void);
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unsigned int cpuamu_read_cpuamcntenclr_el0(void);
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void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
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void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
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int midr_match(unsigned int cpu_midr);
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void cpuamu_context_save(unsigned int nr_counters);
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void cpuamu_context_restore(unsigned int nr_counters);
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#endif /* __ASSEMBLY__ */
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#endif /* __CPUAMU_H__ */
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