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e47ac1fd63
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GIC_V3_H__
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#define __GIC_V3_H__
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/******************************************************************************
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* THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
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* and for GICv3 systems, use the driver in gicv3.h.
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*****************************************************************************/
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#if ERROR_DEPRECATED
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#error " The legacy ARM GIC driver is deprecated."
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#endif
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#include <mmio.h>
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#include <stdint.h>
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#include <types.h>
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/* GICv3 Re-distributor interface registers & shifts */
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#define GICR_PCPUBASE_SHIFT 0x11
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#define GICR_TYPER 0x08
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#define GICR_WAKER 0x14
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/* GICR_WAKER bit definitions */
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#define WAKER_CA (U(1) << 2)
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#define WAKER_PS (U(1) << 1)
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/* GICR_TYPER bit definitions */
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#define GICR_TYPER_AFF_SHIFT 32
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#define GICR_TYPER_AFF_MASK 0xffffffff
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#define GICR_TYPER_LAST (U(1) << 4)
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/* GICv3 ICC_SRE register bit definitions*/
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#define ICC_SRE_EN (U(1) << 3)
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#define ICC_SRE_SRE (U(1) << 0)
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/*******************************************************************************
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* GICv3 defintions
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******************************************************************************/
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#define GICV3_AFFLVL_MASK 0xff
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#define GICV3_AFF0_SHIFT 0
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#define GICV3_AFF1_SHIFT 8
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#define GICV3_AFF2_SHIFT 16
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#define GICV3_AFF3_SHIFT 24
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#define GICV3_AFFINITY_MASK 0xffffffff
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr);
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/*******************************************************************************
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* GIC Redistributor interface accessors
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******************************************************************************/
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static inline uint32_t gicr_read_waker(uintptr_t base)
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{
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return mmio_read_32(base + GICR_WAKER);
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}
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static inline void gicr_write_waker(uintptr_t base, uint32_t val)
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{
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mmio_write_32(base + GICR_WAKER, val);
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}
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static inline uint64_t gicr_read_typer(uintptr_t base)
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{
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return mmio_read_64(base + GICR_TYPER);
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}
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#endif /* __GIC_V3_H__ */
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