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https://github.com/ARM-software/arm-trusted-firmware.git
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7c0a1877e7
At the moment the UART input clock rate is hard coded at compile time. This works as long as the GPU firmware always sets up the same rate, which does not seem to be true for the Raspberry Pi 4. In preparation for being able to change this at runtime, add a base clock parameter to the console setup function. This is still hardcoded for the Raspberry Pi 3. Change-Id: I398bc2f1e9b46f7af9a84cb0b33cbe8e78f2d900 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
241 lines
6.2 KiB
C
241 lines
6.2 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <bl31/interrupt_mgmt.h>
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#include <drivers/console.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <rpi_hw.h>
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#include <rpi_shared.h>
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#ifdef SHARED_RAM_BASE
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#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
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SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#ifdef RPI3_PRELOADED_DTB_BASE
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#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
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MT_MEMORY | MT_RW | MT_NS)
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#endif
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#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
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PLAT_RPI3_FIP_MAX_SIZE, \
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MT_MEMORY | MT_RO | MT_NS)
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#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#ifdef SPD_opteed
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#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
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RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
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RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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/*
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* Table of regions for various BL stages to map using the MMU.
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*/
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#ifdef IMAGE_BL1
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static const mmap_region_t plat_rpi3_mmap[] = {
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#ifdef MAP_SHARED_RAM
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MAP_SHARED_RAM,
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#endif
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MAP_DEVICE0,
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MAP_FIP,
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#ifdef SPD_opteed
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MAP_OPTEE_PAGEABLE,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2
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static const mmap_region_t plat_rpi3_mmap[] = {
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#ifdef MAP_SHARED_RAM
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MAP_SHARED_RAM,
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#endif
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MAP_DEVICE0,
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MAP_FIP,
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MAP_NS_DRAM0,
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#ifdef BL32_BASE
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MAP_BL32_MEM,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL31
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static const mmap_region_t plat_rpi3_mmap[] = {
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#ifdef MAP_SHARED_RAM
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MAP_SHARED_RAM,
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#endif
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MAP_DEVICE0,
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#ifdef RPI3_PRELOADED_DTB_BASE
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MAP_NS_DTB,
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#endif
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#ifdef BL32_BASE
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MAP_BL32_MEM,
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#endif
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{0}
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};
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#endif
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/*******************************************************************************
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* Function that sets up the console
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******************************************************************************/
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static console_16550_t rpi3_console;
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void rpi3_console_init(unsigned int base_clk_rate)
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{
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int console_scope = CONSOLE_FLAG_BOOT;
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#if RPI3_RUNTIME_UART != -1
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console_scope |= CONSOLE_FLAG_RUNTIME;
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#endif
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int rc = console_16550_register(PLAT_RPI3_UART_BASE,
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base_clk_rate,
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PLAT_RPI3_UART_BAUDRATE,
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&rpi3_console);
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if (rc == 0) {
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/*
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* The crash console doesn't use the multi console API, it uses
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* the core console functions directly. It is safe to call panic
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* and let it print debug information.
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*/
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panic();
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}
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console_set_scope(&rpi3_console.console, console_scope);
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}
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/*******************************************************************************
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* Function that sets up the translation tables.
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******************************************************************************/
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void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
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uintptr_t code_start, uintptr_t code_limit,
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uintptr_t rodata_start, uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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, uintptr_t coh_start, uintptr_t coh_limit
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#endif
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)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
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(void *) total_base, (void *) (total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *) code_start, (void *) code_limit);
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mmap_add_region(code_start, code_start,
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code_limit - code_start,
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MT_CODE | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *) rodata_start, (void *) rodata_limit);
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mmap_add_region(rodata_start, rodata_start,
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rodata_limit - rodata_start,
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MT_RO_DATA | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Re-map the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *) coh_start, (void *) coh_limit);
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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mmap_add(plat_rpi3_mmap);
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init_xlat_tables();
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}
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/*******************************************************************************
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* Return entrypoint of BL33.
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******************************************************************************/
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return PLAT_RPI3_NS_IMAGE_OFFSET;
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#endif
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t rpi3_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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uint32_t rpi3_get_spsr_for_bl33_entry(void)
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{
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#if RPI3_BL33_IN_AARCH32
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INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
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return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS);
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#else
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return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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#endif
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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uint32_t plat_ic_get_pending_interrupt_type(void)
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{
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ERROR("rpi3: Interrupt routed to EL3.\n");
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return INTR_TYPE_INVAL;
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}
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uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
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{
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assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
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(type == INTR_TYPE_NS));
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assert(sec_state_is_valid(security_state));
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/* Non-secure interrupts are signalled on the IRQ line always. */
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if (type == INTR_TYPE_NS)
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return __builtin_ctz(SCR_IRQ_BIT);
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/* Secure interrupts are signalled on the FIQ line always. */
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return __builtin_ctz(SCR_FIQ_BIT);
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}
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