mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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afac9681ff
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
199 lines
6.8 KiB
C
199 lines
6.8 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include "agilex_reset_manager.h"
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#include "agilex_mailbox.h"
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#define AGX_RSTMGR_OFST 0xffd11000
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#define AGX_RSTMGR_MPUMODRST_OFST 0x20
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uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
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uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
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/*******************************************************************************
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* plat handler called when a CPU is about to enter standby.
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******************************************************************************/
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void socfpga_cpu_standby(plat_local_state_t cpu_state)
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{
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
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dsb();
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wfi();
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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int socfpga_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
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VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
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if (cpu_id == -1)
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return PSCI_E_INTERN_FAIL;
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*cpuid_release = cpu_id;
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/* release core reset */
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mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
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{
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Prevent interrupts from spuriously waking up this cpu */
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gicv2_cpuif_disable();
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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unsigned int cpu_id = plat_my_core_pos();
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* assert core reset */
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mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Program the gic per-cpu distributor or re-distributor interface */
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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unsigned int cpu_id = plat_my_core_pos();
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* release core reset */
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mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
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1 << cpu_id);
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}
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/*******************************************************************************
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* plat handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 socfpga_system_off(void)
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{
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wfi();
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ERROR("System Off: operation not handled.\n");
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panic();
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}
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static void __dead2 socfpga_system_reset(void)
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{
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INFO("assert Peripheral from Reset\r\n");
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deassert_peripheral_reset();
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mailbox_reset_cold();
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while (1)
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wfi();
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}
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int socfpga_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
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return PSCI_E_SUCCESS;
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}
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int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint)
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{
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VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
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return PSCI_E_SUCCESS;
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}
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void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
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}
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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const plat_psci_ops_t socfpga_psci_pm_ops = {
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.cpu_standby = socfpga_cpu_standby,
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.pwr_domain_on = socfpga_pwr_domain_on,
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.pwr_domain_off = socfpga_pwr_domain_off,
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.pwr_domain_suspend = socfpga_pwr_domain_suspend,
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.pwr_domain_on_finish = socfpga_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish,
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.system_off = socfpga_system_off,
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.system_reset = socfpga_system_reset,
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.validate_power_state = socfpga_validate_power_state,
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.validate_ns_entrypoint = socfpga_validate_ns_entrypoint,
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.get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state
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};
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/*******************************************************************************
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* Export the platform specific power ops.
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const struct plat_psci_ops **psci_ops)
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{
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/* Save warm boot entrypoint.*/
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*agilex_sec_entry = sec_entrypoint;
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*psci_ops = &socfpga_psci_pm_ops;
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return 0;
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}
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