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e655fefcea
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/arm/arm_gicv3_common.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include <plat_imx8.h>
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/* the GICv3 driver only needs to be initialized in EL3 */
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t g01s_interrupt_props[] = {
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INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP1S, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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const gicv3_driver_data_t arm_gic_data = {
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.gicd_base = PLAT_GICD_BASE,
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.gicr_base = PLAT_GICR_BASE,
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.interrupt_props = g01s_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
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};
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void plat_gic_driver_init(void)
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{
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/*
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* the GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in S-EL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#if IMAGE_BL31
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gicv3_driver_init(&arm_gic_data);
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#endif
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}
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static __inline void plat_gicr_exit_sleep(void)
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{
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unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER);
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/*
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* ProcessorSleep bit can ONLY be set to zero when
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* Quiescent bit and Sleep bit are both zero, so
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* need to make sure Quiescent bit and Sleep bit
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* are zero before clearing ProcessorSleep bit.
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*/
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if (val & WAKER_QSC_BIT) {
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mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT);
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/* Wait till the WAKER_QSC_BIT changes to 0 */
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while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U)
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;
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}
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}
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void plat_gic_init(void)
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{
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plat_gicr_exit_sleep();
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void plat_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx)
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{
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/* save the gic rdist/dist context */
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for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
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gicv3_rdistif_save(i, &ctx->rdist_ctx[i]);
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gicv3_distif_save(&ctx->dist_ctx);
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}
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void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx)
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{
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/* restore the gic rdist/dist context */
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gicv3_distif_init_restore(&ctx->dist_ctx);
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for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
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gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]);
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}
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