Baruch Siach 5fb6946ad7 fix(console): fix crash on spin_unlock with cache disabled ...

Current code skips load of spinlock address when cache is disabled. The
following call to spin_unlock stores into the random location that x0
points to.

Move spinlock address load earlier so that x0 is always valid on
spin_unlock call.

Change-Id: Iac640289725dce2518f2fed483d7d36ca748ffe8
Signed-off-by: Baruch Siach <baruch@tkos.co.il>

2022-11-29 03:35:23 +01:00

..

aarch32

feat(debug): add helpers for aborts on AARCH32

2022-10-03 14:42:40 +02:00

aarch64

fix(console): fix crash on spin_unlock with cache disabled

2022-11-29 03:35:23 +01:00

tbbr

Sanitise includes across codebase

2019-01-04 10:43:17 +00:00

plat_bl1_common.c

refactor(measured_boot): remove passing of BL2 hash via device tree

2021-10-12 17:53:47 +01:00

plat_bl_common.c

SMCCC: Introduce function to check SMCCC function availability

2020-07-26 08:16:29 +01:00

plat_gicv2.c

feat(gic): add APIs to raise NS and S-EL1 SGIs

2022-09-14 16:08:29 +02:00

plat_gicv3.c

refactor(libc): clean up dependencies in libc

2022-09-22 13:23:49 +02:00

plat_log_common.c

Sanitise includes across codebase

2019-01-04 10:43:17 +00:00

plat_psci_common.c

Flush dcache when storing timestamp

2020-03-27 09:41:12 -05:00

plat_spmd_manifest.c

fix: libc: use long for 64-bit types on aarch64

2021-11-08 14:41:17 +00:00

ubsan.c

Add UBSAN support and handlers

2019-09-11 14:15:54 +01:00