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https://github.com/ARM-software/arm-trusted-firmware.git
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0ca1d8fba3
This patch is to fix Errata #841119 and #826419 failed apply in linux because of SMMU_CBn_ACTLR register can't be modified in non-secure states. Signed-off-by: Howard Lu <howard.lu@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8
43 lines
956 B
C
43 lines
956 B
C
/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef NXP_SMMU_H
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#define NXP_SMMU_H
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#define SMMU_SCR0 (0x0)
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#define SMMU_NSCR0 (0x400)
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#define SMMU_SACR (0x10)
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#define SCR0_CLIENTPD_MASK 0x00000001
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#define SCR0_USFCFG_MASK 0x00000400
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#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
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static inline void bypass_smmu(uintptr_t smmu_base_addr)
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{
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uint32_t val;
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val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
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~(SCR0_USFCFG_MASK);
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mmio_write_32((smmu_base_addr + SMMU_SCR0), val);
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val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
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~(SCR0_USFCFG_MASK);
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mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
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}
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static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
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{
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uint32_t val;
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val = mmio_read_32((smmu_base_addr + SMMU_SACR));
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val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
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mmio_write_32((smmu_base_addr + SMMU_SACR), val);
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}
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#endif
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