Sona Mathew 2454316c2a fix(cpus): workaround for Cortex-X3 erratum 2070301 ...

Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

2023-10-04 13:45:16 -05:00

..

aarch32

chore: update to use Arm word across TF-A

2023-08-08 15:12:30 +01:00

aarch64

fix(cpus): workaround for Cortex-X3 erratum 2070301

2023-10-04 13:45:16 -05:00

cpu_ops.h

feat(cpus): add a concise way to implement AArch64 errata

2023-05-30 09:31:15 +01:00

errata.h

feat(cpus): make revision procedure call optional

2023-08-07 19:36:56 +01:00

wa_cve_2017_5715.h

chore: update to use Arm word across TF-A

2023-08-08 15:12:30 +01:00

wa_cve_2018_3639.h

chore: update to use Arm word across TF-A

2023-08-08 15:12:30 +01:00

wa_cve_2022_23960.h

chore: update to use Arm word across TF-A

2023-08-08 15:12:30 +01:00