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1a0f9366d8
Since we use a DTB with all platform information to pass this on to a kernel loaded as BL33, we can as well make use of it for our own purposes. Every DT would contain a node for the GIC(v3) interrupt controller, so we can read the base address for the distributor and redistributors from there. This avoids hard coding this information in the code and allows for a more flexible binary. Change-Id: Ic530e223a21a45bc30a07a21048116d5af69e972 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/arm/gic_common.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static const interrupt_prop_t fpga_interrupt_props[] = {
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PLATFORM_G1S_PROPS(INTR_GROUP1S),
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PLATFORM_G0_PROPS(INTR_GROUP0)
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};
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static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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static gicv3_driver_data_t fpga_gicv3_driver_data = {
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.interrupt_props = fpga_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = fpga_rdistif_base_addrs,
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.mpidr_to_core_pos = fpga_mpidr_to_core_pos
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};
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void plat_fpga_gic_init(void)
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{
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const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
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int node, ret;
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node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
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if (node < 0) {
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WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
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return;
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}
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/* TODO: Assuming only empty "ranges;" properties up the bus path. */
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ret = fdt_get_reg_props_by_index(fdt, node, 0,
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&fpga_gicv3_driver_data.gicd_base, NULL);
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if (ret < 0) {
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WARN("Could not read GIC distributor address from DT.\n");
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return;
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}
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ret = fdt_get_reg_props_by_index(fdt, node, 1,
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&fpga_gicv3_driver_data.gicr_base, NULL);
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if (ret < 0) {
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WARN("Could not read GIC redistributor address from DT.\n");
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return;
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}
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gicv3_driver_init(&fpga_gicv3_driver_data);
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void fpga_pwr_gic_on_finish(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void fpga_pwr_gic_off(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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gicv3_rdistif_off(plat_my_core_pos());
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}
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