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ff2743e544
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of clock management, power management, partition management, PAD management etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for clock/power management etc.. This patch adds basic IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
26 lines
842 B
C
26 lines
842 B
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __IMX8_IOMUX_H__
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#define __IMX8_IOMUX_H__
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#define PADRING_IFMUX_EN_SHIFT 31
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#define PADRING_IFMUX_EN_MASK (1 << PADRING_IFMUX_EN_SHIFT)
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#define PADRING_GP_EN_SHIFT 30
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#define PADRING_GP_EN_MASK (1 << PADRING_GP_EN_SHIFT)
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#define PADRING_IFMUX_SHIFT 27
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#define PADRING_IFMUX_MASK (0x7 << PADRING_IFMUX_SHIFT)
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#define PADRING_CONFIG_SHIFT 25
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#define PADRING_CONFIG_MASK (0x3 << PADRING_CONFIG_SHIFT)
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#define PADRING_LPCONFIG_SHIFT 23
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#define PADRING_LPCONFIG_MASK (0x3 << PADRING_LPCONFIG_SHIFT)
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#define PADRING_PULL_SHIFT 5
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#define PADRING_PULL_MASK (0x3 << PADRING_PULL_SHIFT)
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#define PADRING_DSE_SHIFT 0
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#define PADRING_DSE_MASK (0x7 << PADRING_DSE_SHIFT)
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#endif /* __IMX8_IOMUX_H__ */
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