mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-08-20 05:51:01 +02:00
4353bb20cc
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
33 lines
713 B
C
33 lines
713 B
C
/*
|
|
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef __STM32MP1_PWR_H__
|
|
#define __STM32MP1_PWR_H__
|
|
|
|
#include <utils_def.h>
|
|
|
|
#define PWR_CR1 U(0x00)
|
|
#define PWR_CR2 U(0x08)
|
|
#define PWR_CR3 U(0x0C)
|
|
#define PWR_MPUCR U(0x10)
|
|
#define PWR_WKUPCR U(0x20)
|
|
#define PWR_MPUWKUPENR U(0x28)
|
|
|
|
#define PWR_CR1_LPDS BIT(0)
|
|
#define PWR_CR1_LPCFG BIT(1)
|
|
#define PWR_CR1_LVDS BIT(2)
|
|
#define PWR_CR1_DBP BIT(8)
|
|
|
|
#define PWR_CR3_DDRSREN BIT(10)
|
|
#define PWR_CR3_DDRSRDIS BIT(11)
|
|
#define PWR_CR3_DDRRETEN BIT(12)
|
|
|
|
#define PWR_MPUCR_PDDS BIT(0)
|
|
#define PWR_MPUCR_CSTDBYDIS BIT(3)
|
|
#define PWR_MPUCR_CSSF BIT(9)
|
|
|
|
#endif /* __STM32MP1_PWR_H__ */
|