Bipin Ravi b516a6f46c Merge "fix(cpus): use hint instruction for "tsb csync"" into integration

2023-04-14 23:01:32 +02:00

..

aarch32

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

2023-03-15 11:43:14 +00:00

aarch64

Merge "fix(cpus): use hint instruction for "tsb csync"" into integration

2023-04-14 23:01:32 +02:00

cpu-ops.mk

fix(cpus): workaround for Cortex-A78C erratum 1827440

2023-03-21 16:21:38 -05:00

errata_report.c

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

2023-03-15 11:43:14 +00:00