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c52a142b7c
When the TF-A is placed in DDR memory range, the DDR memory range is getting explicitly reserved in the default device tree by TF-A. This creates an error condition in the use case where Device tree is not present or it is present at a different location. To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced. The TF-A will reserve the DDR memory only when a valid DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build. Now the user has options, either manually reserve the desired DDR address range for TF-A in device tree or let TF-A access and modify the device tree, to reserve the DDR address range, in runtime using the build parameter. Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>