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68ac5ed049
If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/sve.h>
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/*
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* Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
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* VECTOR_SIZE = (LEN+1) * 128
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*/
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#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
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static bool sve_supported(void)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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return (features & ID_AA64PFR0_SVE_MASK) == 1U;
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}
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void sve_enable(cpu_context_t *context)
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{
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u_register_t cptr_el3;
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if (!sve_supported()) {
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return;
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}
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cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
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/* Enable access to SVE functionality for all ELs. */
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cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
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write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
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/* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */
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write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
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(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512)));
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}
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