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https://github.com/ARM-software/arm-trusted-firmware.git
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7343505d96
This patch introduces two workarounds for ARMv7 systems. The workarounds need to be applied prior to any `branch` instruction in secure world. This is achieved using a custom vector table where each entry is an `add sp, sp, #1` instruction. On entry to monitor mode, once the sequence of `ADD` instructions is executed, the branch target buffer (BTB) is invalidated. The bottom bits of `SP` are then used to decode the exception entry type. A side effect of this change is that the exception vectors are installed before the CPU specific reset function. This is now consistent with how it is done on AArch64. Note, on AArch32 systems, the exception vectors are typically tightly integrated with the secure payload (e.g. the Trusted OS). This workaround will need porting to each secure payload that requires it. The patch to modify the AArch32 per-cpu vbar to the corresponding workaround vector table according to the CPU type will be done in a later patch. Change-Id: I5786872497d359e496ebe0757e8017fa98f753fa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
166 lines
5.0 KiB
C
166 lines
5.0 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_HELPERS_H__
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#define __SMCC_HELPERS_H__
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#include <smcc.h>
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/* These are offsets to registers in smc_ctx_t */
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#define SMC_CTX_GPREG_R0 0x0
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#define SMC_CTX_GPREG_R1 0x4
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#define SMC_CTX_GPREG_R2 0x8
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#define SMC_CTX_GPREG_R3 0xC
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#define SMC_CTX_GPREG_R4 0x10
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#define SMC_CTX_GPREG_R5 0x14
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#define SMC_CTX_SP_USR 0x34
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#define SMC_CTX_SPSR_MON 0x78
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#define SMC_CTX_SP_MON 0x7C
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#define SMC_CTX_LR_MON 0x80
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#define SMC_CTX_SCR 0x84
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#define SMC_CTX_PMCR 0x88
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#define SMC_CTX_SIZE 0x90
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <types.h>
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/*
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* The generic structure to save arguments and callee saved registers during
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* an SMC. Also this structure is used to store the result return values after
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* the completion of SMC service.
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*/
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typedef struct smc_ctx {
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u_register_t r0;
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u_register_t r1;
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u_register_t r2;
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u_register_t r3;
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u_register_t r4;
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u_register_t r5;
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u_register_t r6;
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u_register_t r7;
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u_register_t r8;
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u_register_t r9;
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u_register_t r10;
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u_register_t r11;
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u_register_t r12;
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/* spsr_usr doesn't exist */
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u_register_t sp_usr;
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u_register_t lr_usr;
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u_register_t spsr_irq;
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u_register_t sp_irq;
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u_register_t lr_irq;
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u_register_t spsr_fiq;
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u_register_t sp_fiq;
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u_register_t lr_fiq;
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u_register_t spsr_svc;
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u_register_t sp_svc;
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u_register_t lr_svc;
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u_register_t spsr_abt;
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u_register_t sp_abt;
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u_register_t lr_abt;
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u_register_t spsr_und;
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u_register_t sp_und;
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u_register_t lr_und;
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u_register_t spsr_mon;
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/*
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* `sp_mon` will point to the C runtime stack in monitor mode. But prior
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* to exit from SMC, this will point to the `smc_ctx_t` so that
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* on next entry due to SMC, the `smc_ctx_t` can be easily accessed.
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*/
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u_register_t sp_mon;
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u_register_t lr_mon;
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u_register_t scr;
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u_register_t pmcr;
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/*
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* The workaround for CVE-2017-5715 requires storing information in
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* the bottom 3 bits of the stack pointer. Add a padding field to
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* force the size of the struct to be a multiple of 8.
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*/
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u_register_t pad;
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} smc_ctx_t __aligned(8);
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/*
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* Compile time assertions related to the 'smc_context' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
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assert_smc_ctx_greg_r0_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
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assert_smc_ctx_greg_r1_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
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assert_smc_ctx_greg_r2_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
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assert_smc_ctx_greg_r3_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
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assert_smc_ctx_greg_r4_offset_mismatch);
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CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
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assert_smc_ctx_sp_usr_offset_mismatch);
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CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
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assert_smc_ctx_lr_mon_offset_mismatch);
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CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
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assert_smc_ctx_spsr_mon_offset_mismatch);
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CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned);
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CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch);
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/* Convenience macros to return from SMC handler */
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#define SMC_RET0(_h) { \
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return (uintptr_t)(_h); \
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}
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#define SMC_RET1(_h, _r0) { \
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((smc_ctx_t *)(_h))->r0 = (_r0); \
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SMC_RET0(_h); \
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}
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#define SMC_RET2(_h, _r0, _r1) { \
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((smc_ctx_t *)(_h))->r1 = (_r1); \
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SMC_RET1(_h, (_r0)); \
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}
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#define SMC_RET3(_h, _r0, _r1, _r2) { \
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((smc_ctx_t *)(_h))->r2 = (_r2); \
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SMC_RET2(_h, (_r0), (_r1)); \
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}
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#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \
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((smc_ctx_t *)(_h))->r3 = (_r3); \
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SMC_RET3(_h, (_r0), (_r1), (_r2)); \
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}
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/* Return a UUID in the SMC return registers */
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#define SMC_UUID_RET(_h, _uuid) \
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SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
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((const uint32_t *) &(_uuid))[1], \
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((const uint32_t *) &(_uuid))[2], \
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((const uint32_t *) &(_uuid))[3])
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/*
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* Helper macro to retrieve the SMC parameters from smc_ctx_t.
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*/
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#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \
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_r1 = ((smc_ctx_t *)_hdl)->r1; \
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_r2 = ((smc_ctx_t *)_hdl)->r2; \
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_r3 = ((smc_ctx_t *)_hdl)->r3; \
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_r4 = ((smc_ctx_t *)_hdl)->r4; \
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}
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/* ------------------------------------------------------------------------
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* Helper APIs for setting and retrieving appropriate `smc_ctx_t`.
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* These functions need to implemented by the BL including this library.
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* ------------------------------------------------------------------------
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*/
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/* Get the pointer to `smc_ctx_t` corresponding to the security state. */
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void *smc_get_ctx(unsigned int security_state);
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/* Set the next `smc_ctx_t` corresponding to the security state. */
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void smc_set_next_ctx(unsigned int security_state);
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/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
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void *smc_get_next_ctx(void);
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#endif /*__ASSEMBLY__*/
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#endif /* __SMCC_HELPERS_H__ */
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