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3d732e23e7
On GICv3 systems, as a side effect of adding provision to handle EL3
interrupts (unconditionally routing FIQs to EL3), pending Non-secure
interrupts (signalled as FIQs) may preempt execution in lower Secure ELs
[1]. This will inadvertently disrupt the semantics of Fast SMC
(previously called Atomic SMC) calls.
To retain semantics of Fast SMCs, the GIC PMR must be programmed to
prevent Non-secure interrupts from preempting Secure execution. To that
effect, two new functions in the Exception Handling Framework subscribe
to events introduced in an earlier commit:
- Upon 'cm_exited_normal_world', the Non-secure PMR is stashed, and
the PMR is programmed to the highest Non-secure interrupt priority.
- Upon 'cm_entering_normal_world', the previously stashed Non-secure
PMR is restored.
The above sequence however prevents Yielding SMCs from being preempted
by Non-secure interrupts as intended. To facilitate this, the public API
exc_allow_ns_preemption() is introduced that programs the PMR to the
original Non-secure PMR value. Another API
exc_is_ns_preemption_allowed() is also introduced to check if
exc_allow_ns_preemption() had been called previously.
API documentation to follow.
[1] On GICv2 systems, this isn't a problem as, unlike GICv3, pending NS
IRQs during Secure execution are signalled as IRQs, which aren't
routed to EL3.
Change-Id: Ief96b162b0067179b1012332cd991ee1b3051dd0
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __EHF_H__
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#define __EHF_H__
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#include <utils_def.h>
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/* Valid priorities set bit 0 of the priority handler. */
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#define _EHF_PRI_VALID (((uintptr_t) 1) << 0)
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/* Marker for no handler registered for a valid priority */
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#define _EHF_NO_HANDLER (0 | _EHF_PRI_VALID)
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/* Extract the specified number of top bits from 7 lower bits of priority */
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#define EHF_PRI_TO_IDX(pri, plat_bits) \
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((pri & 0x7f) >> (7 - plat_bits))
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/* Install exception priority descriptor at a suitable index */
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#define EHF_PRI_DESC(plat_bits, priority) \
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[EHF_PRI_TO_IDX(priority, plat_bits)] = { \
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.ehf_handler = _EHF_NO_HANDLER, \
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}
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/* Macro for platforms to regiter its exception priorities */
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#define EHF_REGISTER_PRIORITIES(priorities, num, bits) \
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const ehf_priorities_t exception_data = { \
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.num_priorities = num, \
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.ehf_priorities = priorities, \
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.pri_bits = bits, \
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}
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/*
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* Priority stack, managed as a bitmap.
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*
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* Currently only supports 32 priority levels, allowing platforms to use up to 5
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* top bits of priority. But the type can be changed to uint64_t should need
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* arise to support 64 priority levels, allowing platforms to use up to 6 top
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* bits of priority.
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*/
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typedef uint32_t ehf_pri_bits_t;
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/*
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* Per-PE exception data. The data for each PE is kept as a per-CPU data field.
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* See cpu_data.h.
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*/
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typedef struct {
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ehf_pri_bits_t active_pri_bits;
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/* Priority mask value before any priority levels were active */
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uint8_t init_pri_mask;
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/* Non-secure priority mask value stashed during Secure execution */
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uint8_t ns_pri_mask;
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} __aligned(sizeof(uint64_t)) pe_exc_data_t;
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typedef int (*ehf_handler_t)(uint32_t intr_raw, uint32_t flags, void *handle,
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void *cookie);
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typedef struct ehf_pri_desc {
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/*
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* 4-byte-aligned exception handler. Bit 0 indicates the corresponding
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* priority level is valid. This is effectively of ehf_handler_t type,
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* but left as uintptr_t in order to make pointer arithmetic convenient.
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*/
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uintptr_t ehf_handler;
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} ehf_pri_desc_t;
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typedef struct ehf_priorities {
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ehf_pri_desc_t *ehf_priorities;
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unsigned int num_priorities;
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int pri_bits;
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} ehf_priorities_t;
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void ehf_init(void);
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void ehf_activate_priority(unsigned int priority);
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void ehf_deactivate_priority(unsigned int priority);
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void ehf_register_priority_handler(unsigned int pri, ehf_handler_t handler);
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void ehf_allow_ns_preemption(void);
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unsigned int ehf_is_ns_preemption_allowed(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __EHF_H__ */
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