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https://github.com/ARM-software/arm-trusted-firmware.git
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ee1ebbd18e
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl31.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <errno.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include "zynqmp_private.h"
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#define BL31_END (unsigned long)(&__BL31_END__)
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/*
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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*/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type));
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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return &bl32_image_ep_info;
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}
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/*
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* Perform any BL31 specific platform actions. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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* are lost (potentially). This needs to be done before the MMU is initialized
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* so that the memory layout can be used while creating page tables.
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*/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* Initialize the console to provide early debug support */
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console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
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ZYNQMP_UART_BAUDRATE);
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/* Initialize the platform config for future decision making */
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zynqmp_config_setup();
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(from_bl2 == NULL);
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assert(plat_params_from_bl2 == NULL);
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/*
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* Do initial security configuration to allow DRAM/device access. On
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* Base ZYNQMP only DRAM security is programmable (via TrustZone), but
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* other platforms might have more programmable security devices
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* present.
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*/
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/* Populate common information for BL32 and BL33 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
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/* use build time defaults in JTAG boot mode */
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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} else {
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/* use parameters from FSBL */
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fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info);
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}
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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}
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/* Enable the test setup */
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#ifndef ZYNQMP_TESTING
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static void zynqmp_testing_setup(void) { }
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#else
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static void zynqmp_testing_setup(void)
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{
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uint32_t actlr_el3, actlr_el2;
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/* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
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actlr_el3 = read_actlr_el3();
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actlr_el2 = read_actlr_el2();
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actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
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actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
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write_actlr_el3(actlr_el3);
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write_actlr_el2(actlr_el2);
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}
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#endif
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void bl31_platform_setup(void)
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{
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/* Initialize the gic cpu and distributor interfaces */
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plat_arm_gic_driver_init();
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plat_arm_gic_init();
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zynqmp_testing_setup();
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}
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void bl31_plat_runtime_setup(void)
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{
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}
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/*
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* Perform the very early platform specific architectural setup here.
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*/
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void bl31_plat_arch_setup(void)
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{
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plat_arm_interconnect_init();
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plat_arm_interconnect_enter_coherency();
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arm_setup_page_tables(BL31_BASE,
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BL31_END - BL31_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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enable_mmu_el3(0);
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}
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