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https://github.com/ARM-software/arm-trusted-firmware.git
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e2af1cadf7
OP-TEE may have extra images to be loaded. Load them one by one and do the parsing. In this patch, ARM TF need to load up to 3 images for OP-TEE: header, pager and pages images. Header image is the info about optee os and images. Pager image include pager code and data. Paged image include the paging parts using virtual memory. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
110 lines
3.1 KiB
Makefile
110 lines
3.1 KiB
Makefile
#
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# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/libfdt/libfdt.mk
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# Enable new version of image loading on QEMU platforms
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LOAD_IMAGE_V2 := 1
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ifeq ($(NEED_BL32),yes)
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$(eval $(call add_define,QEMU_LOAD_BL32))
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endif
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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-Iplat/qemu/include \
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-Iinclude/common/tbbr
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# Use translation tables library v2 by default
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ARM_XLAT_TABLES_LIB_V1 := 0
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$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
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$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
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PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \
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drivers/arm/pl011/aarch64/pl011_console.S
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ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
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PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c
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else
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
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endif
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BL1_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/aarch64/semihosting_call.S \
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plat/qemu/qemu_io_storage.c \
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lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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plat/qemu/aarch64/plat_helpers.S \
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plat/qemu/qemu_bl1_setup.c
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BL2_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/aarch64/semihosting_call.S\
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plat/qemu/qemu_io_storage.c \
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plat/qemu/aarch64/plat_helpers.S \
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plat/qemu/qemu_bl2_setup.c \
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plat/qemu/dt.c \
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$(LIBFDT_SRCS)
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ifeq (${LOAD_IMAGE_V2},1)
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BL2_SOURCES += plat/qemu/qemu_bl2_mem_params_desc.c \
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plat/qemu/qemu_image_load.c \
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common/desc_image_load.c
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endif
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ifeq (${SPD},opteed)
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BL2_SOURCES += lib/optee/optee_utils.c
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endif
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BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/common/gic_common.c \
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plat/common/plat_psci_common.c \
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plat/qemu/qemu_pm.c \
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plat/qemu/topology.c \
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plat/qemu/aarch64/plat_helpers.S \
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plat/qemu/qemu_bl31_setup.c \
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plat/qemu/qemu_gic.c
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# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
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# in the FIP if the platform requires.
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ifneq ($(BL32_EXTRA1),)
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$(eval $(call FIP_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
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endif
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ifneq ($(BL32_EXTRA2),)
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$(eval $(call FIP_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
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endif
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# Disable the PSCI platform compatibility layer
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ENABLE_PLAT_COMPAT := 0
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BL32_RAM_LOCATION := tdram
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ifeq (${BL32_RAM_LOCATION}, tsram)
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BL32_RAM_LOCATION_ID = SEC_SRAM_ID
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else ifeq (${BL32_RAM_LOCATION}, tdram)
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BL32_RAM_LOCATION_ID = SEC_DRAM_ID
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else
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$(error "Unsupported BL32_RAM_LOCATION value")
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endif
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# Process flags
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$(eval $(call add_define,BL32_RAM_LOCATION_ID))
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