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aea772dd7a
DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
8 lines
140 B
C
8 lines
140 B
C
/*
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* Copyright (c) 2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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void agx_mmc_init(void);
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