Sandrine Bailleux c00b06a41b Merge "fix(intel): fix sp_timer0 is not disabled in firewall on Agilex" into integration

2022-11-28 15:03:16 +01:00

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aarch64

feat(intel): add macro to switch between different UART PORT

2022-04-05 14:25:30 +08:00

drivers

feat(intel): enable firewall for OCRAM in BL31

2022-04-28 19:08:35 +08:00

include

fix(intel): fix UART baud rate and clock

2022-11-21 13:50:10 +01:00

sip

fix(intel): fix Mac verify update and finalize for return response data

2022-09-16 02:49:01 +08:00

soc

fix(intel): fix sp_timer0 is not disabled in firewall on Agilex

2022-11-22 23:55:02 +08:00

bl2_plat_mem_params_desc.c

chore: use tabs for indentation

2022-08-30 19:40:44 +02:00

socfpga_delay_timer.c

fix(intel): remove unused printout

2022-05-13 16:46:25 +08:00

socfpga_image_load.c

intel: Implement platform specific system reset 2

2019-12-30 10:17:04 +08:00

socfpga_psci.c

fix(intel): fix ECC Double Bit Error handling

2022-03-09 09:14:16 +08:00

socfpga_sip_svc_v2.c

feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands

2022-05-11 17:45:37 +08:00

socfpga_sip_svc.c

fix(intel): remove checking on TEMP and VOLT checking for HWMON

2022-11-22 23:56:06 +08:00

socfpga_storage.c

intel: Refactor common platform code [2/5]

2019-11-28 12:47:58 +08:00

socfpga_topology.c

intel: Platform common code refactor

2019-08-01 16:39:27 +08:00