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https://github.com/ARM-software/arm-trusted-firmware.git
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f3ff9f77d3
The Amlogic Meson S905 is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested in an ODROID-C2. Change-Id: Ia4bc82d7aca42a69d6b118b947279f82b3f6c6da Tested-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <ep_info.h>
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#include <interrupt_mgmt.h>
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#include <meson_console.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <xlat_tables_v2.h>
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/*******************************************************************************
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* Platform memory map regions
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******************************************************************************/
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#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
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GXBB_NSDRAM0_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
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GXBB_NSDRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
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GXBB_SEC_DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
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GXBB_SEC_DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
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GXBB_TZRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
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GXBB_SEC_DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
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GXBB_SEC_DEVICE3_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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static const mmap_region_t gxbb_mmap[] = {
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MAP_NSDRAM0,
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MAP_NSDRAM1,
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MAP_SEC_DEVICE0,
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MAP_SEC_DEVICE1,
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MAP_TZRAM,
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MAP_SEC_DEVICE2,
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MAP_SEC_DEVICE3,
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{0}
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};
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/*******************************************************************************
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* Per-image regions
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******************************************************************************/
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#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
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BL31_END - BL31_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
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BL_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE)
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#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
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BL_RO_DATA_END - BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*******************************************************************************
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* Function that sets up the translation tables.
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******************************************************************************/
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void gxbb_setup_page_tables(void)
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{
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#if IMAGE_BL31
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const mmap_region_t gxbb_bl_mmap[] = {
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MAP_BL31,
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MAP_BL_CODE,
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MAP_BL_RO_DATA,
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#if USE_COHERENT_MEM
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MAP_BL_COHERENT,
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#endif
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{0}
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};
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#endif
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mmap_add(gxbb_bl_mmap);
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mmap_add(gxbb_mmap);
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init_xlat_tables();
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}
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/*******************************************************************************
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* Function that sets up the console
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******************************************************************************/
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static console_meson_t gxbb_console;
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void gxbb_console_init(void)
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{
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int rc = console_meson_register(GXBB_UART0_AO_BASE,
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GXBB_UART0_AO_CLK_IN_HZ,
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GXBB_UART_BAUDRATE,
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&gxbb_console);
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if (rc == 0) {
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/*
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* The crash console doesn't use the multi console API, it uses
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* the core console functions directly. It is safe to call panic
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* and let it print debug information.
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*/
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panic();
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}
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console_set_scope(&gxbb_console.console,
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CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
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}
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/*******************************************************************************
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* Function that returns the system counter frequency
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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{
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uint32_t val;
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val = mmio_read_32(GXBB_SYS_CPU_CFG7);
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val &= 0xFDFFFFFF;
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mmio_write_32(GXBB_SYS_CPU_CFG7, val);
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val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
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val &= 0xFFFFFE00;
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mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
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return GXBB_OSC24M_CLK_IN_HZ;
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}
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