mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-09-13 01:31:29 +02:00
f5c58af653
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
62 lines
1.7 KiB
ArmAsm
62 lines
1.7 KiB
ArmAsm
/*
|
|
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <arch.h>
|
|
#include <asm_macros.S>
|
|
#include <platform_def.h>
|
|
#include <cpu_macros.S>
|
|
|
|
.globl plat_arm_calc_core_pos
|
|
.globl plat_reset_handler
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
|
*
|
|
* Function to calculate the core position on TC0.
|
|
*
|
|
* (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
|
|
* (CPUId * PLAT_MAX_PE_PER_CPU) +
|
|
* ThreadId
|
|
*
|
|
* which can be simplified as:
|
|
*
|
|
* ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
|
|
* + ThreadId
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
func plat_arm_calc_core_pos
|
|
/*
|
|
* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
|
|
* look as if in a multi-threaded implementation.
|
|
*/
|
|
tst x0, #MPIDR_MT_MASK
|
|
lsl x3, x0, #MPIDR_AFFINITY_BITS
|
|
csel x3, x3, x0, eq
|
|
|
|
/* Extract individual affinity fields from MPIDR */
|
|
ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
|
ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
|
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
|
|
|
/* Compute linear position */
|
|
mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
|
|
madd x1, x2, x4, x1
|
|
mov x5, #PLAT_MAX_PE_PER_CPU
|
|
madd x0, x1, x5, x0
|
|
ret
|
|
endfunc plat_arm_calc_core_pos
|
|
|
|
/* -----------------------------------------------------
|
|
* void plat_reset_handler(void);
|
|
*
|
|
* Determine the CPU MIDR and disable power down bit for
|
|
* that CPU.
|
|
* -----------------------------------------------------
|
|
*/
|
|
func plat_reset_handler
|
|
ret
|
|
endfunc plat_reset_handler
|