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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
110 lines
3.5 KiB
C
110 lines
3.5 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VERSAL_DEF_H
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#define VERSAL_DEF_H
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#include <plat/common/common_def.h>
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/* List all consoles */
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#define VERSAL_CONSOLE_ID_pl011 1
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#define VERSAL_CONSOLE_ID_pl011_0 1
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#define VERSAL_CONSOLE_ID_pl011_1 2
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#define VERSAL_CONSOLE_ID_dcc 3
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#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
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/* List all supported platforms */
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#define VERSAL_PLATFORM_ID_versal_virt 1
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#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
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/* Firmware Image Package */
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#define VERSAL_PRIMARY_CPU 0
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/*******************************************************************************
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* memory map related constants
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******************************************************************************/
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#define DEVICE0_BASE 0xFF000000
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#define DEVICE0_SIZE 0x00E00000
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#define DEVICE1_BASE 0xF9000000
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#define DEVICE1_SIZE 0x00800000
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/* CRL */
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#define VERSAL_CRL 0xFF5E0000
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#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114)
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#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
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#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
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#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
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#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25)
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#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
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/* IOU SCNTRS */
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#define VERSAL_IOU_SCNTRS 0xFF140000
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#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0)
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#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20)
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#define VERSAL_IOU_SCNTRS_CONTROL_EN 1
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/*******************************************************************************
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* IRQ constants
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******************************************************************************/
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#define VERSAL_IRQ_SEC_PHY_TIMER 29
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define VERSAL_UART0_BASE 0xFF000000
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#define VERSAL_UART1_BASE 0xFF010000
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#if VERSAL_CONSOLE_IS(pl011)
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# define VERSAL_UART_BASE VERSAL_UART0_BASE
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#elif VERSAL_CONSOLE_IS(pl011_1)
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# define VERSAL_UART_BASE VERSAL_UART1_BASE
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#else
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# error "invalid VERSAL_CONSOLE"
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#endif
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#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
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#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
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#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
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/*******************************************************************************
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* Platform related constants
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******************************************************************************/
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#if VERSAL_PLATFORM_IS(versal_virt)
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# define PLATFORM_NAME "Versal Virt"
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# define VERSAL_UART_CLOCK 25000000
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# define VERSAL_UART_BAUDRATE 115200
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# define VERSAL_CPU_CLOCK 62500000
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#endif
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/* Access control register defines */
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
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#define CRF_BASE 0xFD1A0000
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#define CRF_SIZE 0x00600000
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/* CRF registers and bitfields */
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#define CRF_RST_APU (CRF_BASE + 0X00000300)
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#define CRF_RST_APU_ACPU_RESET (1 << 0)
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#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
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/* APU registers and bitfields */
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#define FPD_APU_BASE 0xFD5C0000
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#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20)
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#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40)
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#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44)
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#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90)
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#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
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#endif /* VERSAL_DEF_H */
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